[bug] CudfWindow streaming disk-spill tests see 1 write instead of 3

[sperlingxx]

Highlight (by human-in-loop)

1. This is Flux-added test case.
2. This is a test case error which was introduced in feat(cudf): Support multi-column RANGE Window aggregates #20 , NOT a production code error.

Problem

Part of umbrella #100 (velox_cudf_adapter_operator_test).

AdapterOperatorTest.streamingFullPartitionCountSpillsActivePartition and AdapterOperatorTest.streamingRangeSumSpillsActivePeer expect CudfWindow::testingStreamingSpillWrites() >= 3 (GPU table written as Parquet under the task spill directory). On current dev both see 1 write. Query results are still correct.

These cases feed three tiny Values batches and cap the streaming window at 1 byte so the still-open partition / RANGE peer must spill on each addInput, then replay from disk.

Root cause

Values stays on CPU. CudfFromVelox buffers until velox.cudf.gpu_batch_size_rows (default 100000) or noMoreInput(). Six rows never hit that threshold, so CudfWindow receives one coalesced GPU batch after end of input and spills only the trailing group.

The tests were added in #20 when Values was still replaced by CudfValues (one GPU batch per Values vector). After GPU operators were reconciled with upstream, that replacement went away and the spill counts collapsed to 1.

This is not HMB / host-memory spill. spillActiveRows() writes Parquet to the task spill directory.

Expected behavior

With a 1-byte active-row cap and three input batches:

• full-partition COUNT spills the still-open k=1 partition on each add, then replays so every k=1 row sees count 4;
• multi-column RANGE SUM spills the still-open peer (a=10, b=5) on each add, then replays so the peer sum stays 6 and the following running sum stays 10;
• testingStreamingSpillWrites() >= 3 and testingStreamingSpillCleanups() == 1.

Acceptance criteria

• Keep each Values batch as its own GPU input in these two tests (velox.cudf.gpu_batch_size_rows=1).
• Both spill tests pass, including disk-spill write/cleanup counters.
• The rest of velox_cudf_adapter_operator_test still passes.

Validation

Reproduced and verified on HPDA dev 28798f623 (CUDA SM 86):

• unfixed: both tests actual: 1 vs 3;
• fixed: the two spill tests pass, and the full binary is 18/18.

Prepared with assistance from Cursor.

[sperlingxx]

Fix PR: #106