Skip to content

Releases: IanSteveC/ps_claude_opt

V1.1 — CUDA (V100) speedups + Radeon VII (gfx906) HIP optimization

Choose a tag to compare

@IanSteveC IanSteveC released this 15 Jul 20:49

Performance pass on both the CUDA and HIP backends, plus Windows HIP build fixes. Drop-in update to V1.0 — every change is byte-identical or within reference tolerance, and no accuracy path (period/rms/chi², dark-area/lambda/beta) moves.

What's new since V1.0

CUDA (NVIDIA)

  • curve2 rank-K tile product form restored on ≥1:2-FP64 parts (sm_60/70/80/90/100): the redundant-per-lane FP64 form rides the idle DP pipe instead of the saturated MIO/shuffle path, __dmul_rn-fenced so rounding matches exactly (−17%).
  • Split the fused M12 I1 curve kernels into curve1/curve2 halves: the fused kernel's register footprint capped occupancy; dytemp already round-trips through global memory between the phases, so the split adds no traffic (−7%).

HIP (AMD, Radeon VII / gfx906)

  • wave64 curve1 — one physical wave per trial (two point-pairs across the half-waves) instead of packing two unrelated trials per wave, removing the cross-bid divergence that dominated the hot kernel (−16%).
  • curve2 LDS shave — per-lane registers replace the shared broadcast arrays, lifting the tile kernels to 4 workgroups/CU (−2.5%).
  • Windows HIP build fixeshipDeviceAttributeWarpSize in the no-ROCm-headers shim and modbuild/bin2c.py now tracked, so that target builds from a clean clone; plus a df64/FP32 compile fix.

RDNA (wave32) and CDNA are functionally unchanged; the CUDA and HIP arch-specific paths are gated so every target keeps its best variant. See OPTIMIZATION_NOTES.md for the engineering log.

V1.0 — optimized CUDA app for Linux x64 + aarch64 (BOINC anonymous platform)

Choose a tag to compare

@IanSteveC IanSteveC released this 04 Jul 14:32

Optimized CUDA build of the AsteroidsAtHome period_search application (asteroid lightcurve inversion), packaged for BOINC anonymous platform use on Linux. Roughly 7× faster than the original CUDA build on data-center GPUs (Tesla V100, input_239_1: 168 s → ~23 s) with arch-gated code paths so consumer GeForce and Jetson parts each get their best FP64-economy variant (Jetson Orin Nano full workunit: ~34.6 min). Scientific outputs are bit-exact or validated within reference tolerance against the stock application — see OPTIMIZATION_NOTES.md for the complete engineering log.

Downloads

archive platform plan class GPU support (embedded SASS)
periodsearch_cuda-opt_linux_x64.zip x86_64-pc-linux-gnu cuda1200_linux sm_50 – sm_120 (Maxwell → Blackwell)
periodsearch_cuda-opt_linux_aarch64.zip aarch64-unknown-linux-gnu cuda129 sm_60 – sm_120 incl. Jetson Xavier (sm_72) and Orin (sm_87)
periodsearch_cuda-opt_win64.zip windows_x86_64 cuda1200_win sm_50 – sm_120 (byte-identical GPU code to the x64 Linux app)
periodsearch_HIP-opt_linux_x64.zip x86_64-pc-linux-gnu (AMD/ROCm) hip_amd_linux gfx906/908/90a, gfx101x, gfx103x, gfx110x, gfx120x (GCN5/CDNA + RDNA1-4, 16 targets)
periodsearch_HIP-opt_win64.zip windows_x86_64 (AMD) hip_amd_win same 16 gfx targets; MinGW cross-build, amdhip64.dll loaded dynamically (needs only the AMD driver, no ROCm SDK)

sha256:

4789814ab857268dcc0f546dc9817fbc399cd6daa20ee9695d09b6c69742a0c3  periodsearch_cuda-opt_linux_x64.zip
3d55dc9a9039be4a73aff6900091566e77429ea7b0b31d7f0275c4bd145c8fb4  periodsearch_cuda-opt_win64.zip
a9eb226594c58a10043dd00b861d9acdfdd37166903310d690c4b9455105e049  periodsearch_HIP-opt_linux_x64.zip
bb83aaecdc34b46f9fdbb609e723dbaed99be131d1de6d2e5f7068a749e222ec  periodsearch_HIP-opt_win64.zip
cfc542206a19af58036c9b5d490782c9dd56a26fc237c4a21d226b9b52ebc1c0  periodsearch_cuda-opt_linux_aarch64.zip

Highlights

  • Pole-merged grid: the 10 pole trials of each frequency run concurrently (bit-exact, ~2×).
  • Memory-locality rewrite: per-block Dg matrix eliminated via Dg = Dsph · g; shared transposed basis matrix; transposed dytemp; in-shared-memory Gauss solver.
  • Arch-gated FAT_FP64: data-center GPUs (≥1:2 FP64) use the FP32 basis mirror + uniform-DP products; GeForce/Jetson keep the FP64 table with lane-parallel geometry batching.
  • Blackwell (RTX 50-series) fixes: sm_120 SASS generated from compute_89 PTX (avoids a ptxas codegen bug that produced intermittent NaN χ²), plus a clamp on the solar-phase acos argument that fixed all-NaN outputs on 5060 Ti / 5070.
  • Built with CUDA 12.9.1 — requires an NVIDIA driver with CUDA 12.9 support.
  • AMD build (HIP/ROCm): the same optimized app ported to HIP for AMD GPUs on Linux (periodsearch_HIP-opt_linux_x64.zip, plan class hip_amd_linux, coproc type ATI). Correct on wave64 (Radeon VII) and wave32 (RDNA); ~2.2× faster than the project's OpenCL app on the Radeon VII. Unlike the CUDA builds it needs a ROCm 7.x runtime installed (not just the driver — HIP's runtime can't be statically linked), plus the amdgpu kernel driver with KFD.
  • Windows build: cross-compiled from Linux with MinGW-w64 over the CUDA driver API (build_win.sh) — no CUDA toolkit or Visual C++ redistributables needed on the target, only an NVIDIA driver (nvcuda.dll). Its embedded GPU code is extracted from the Linux build's device link, verified byte-identical per architecture. Validated on RTX 3080 Ti: results match the Linux/ROCm reference (179/182 lines bit-identical, rest last-digit rounding).

Install (BOINC anonymous platform)

  1. Stop the BOINC client.
  2. Unzip into your project directory (.../projects/asteroidsathome.net_boinc/). Each archive contains the executable and a ready app_info.xml — if you already have an app_info.xml, back it up and merge.
  3. Restart BOINC.

Unofficial build: workunits are still validated server-side against the project's canonical results, so an incompatibility shows up as an invalid result, not bad science.