V1.1 — CUDA (V100) speedups + Radeon VII (gfx906) HIP optimization

Performance pass on both the CUDA and HIP backends, plus Windows HIP build fixes. Drop-in update to V1.0 — every change is byte-identical or within reference tolerance, and no accuracy path (period/rms/chi², dark-area/lambda/beta) moves.

What's new since V1.0

CUDA (NVIDIA)

• curve2 rank-K tile product form restored on ≥1:2-FP64 parts (sm_60/70/80/90/100): the redundant-per-lane FP64 form rides the idle DP pipe instead of the saturated MIO/shuffle path, __dmul_rn-fenced so rounding matches exactly (−17%).
• Split the fused M12 I1 curve kernels into curve1/curve2 halves: the fused kernel's register footprint capped occupancy; dytemp already round-trips through global memory between the phases, so the split adds no traffic (−7%).

HIP (AMD, Radeon VII / gfx906)

• wave64 curve1 — one physical wave per trial (two point-pairs across the half-waves) instead of packing two unrelated trials per wave, removing the cross-bid divergence that dominated the hot kernel (−16%).
• curve2 LDS shave — per-lane registers replace the shared broadcast arrays, lifting the tile kernels to 4 workgroups/CU (−2.5%).
• Windows HIP build fixes — hipDeviceAttributeWarpSize in the no-ROCm-headers shim and modbuild/bin2c.py now tracked, so that target builds from a clean clone; plus a df64/FP32 compile fix.

RDNA (wave32) and CDNA are functionally unchanged; the CUDA and HIP arch-specific paths are gated so every target keeps its best variant. See OPTIMIZATION_NOTES.md for the engineering log.