Gamma Code Encoder

VHDL implementation of a gamma code encoder developed as part of a university course in digital design.

Description

The project implements a gamma code encoder using a finite state machine (FSM) in VHDL. The design was simulated in ModelSim using testbenches to verify correct functionality and demonstrated on an FPGA. The project report was submitted anonymously in accordance with exam requirement.

Repository contents

• src/ – VHDL source files and testbenches
• gamma-code-encoder-report.pdf – Project report with design description and verification results

Language and Tools

• VHDL
• ModelSim
• Quartus Prime