Tutorial FPL2015

Michael Adler edited this page Sep 1, 2015 · 4 revisions

The LEAP Run-Time System: Rapid System Integration of Your HLS Kernels

Tuesday, September 1st, 13:30, Imperial College

Do you find yourself bogged down in FPGA plumbing, focused on the mechanics of moving data instead of on your algorithms? Are you using an HLS compiler but tired of building FPGA-side memory hierarchies? These problems are not unique to hardware. Analogous software problems were solved decades ago. We don't manage locks for shared memory access directly in Python. Developers compose Python with complex underlying primitives that are debugged once and shared across languages. High level languages are great for expressing abstract programs. A full system also requires glue logic and low-level, high-performance components.

The LEAP operating environment for FPGAs provides composable components and services for algorithms spanning one or more FPGAs and for hybrid algorithms combining FPGAs and software. LEAP APIs remain consistent across a variety of platforms, enabling application portability. LEAP separates the problem of specifying an algorithm from the problem of building a supporting run-time system. The LEAP programming model allows both hand-coders and HLS compiler users to focus on their own applications.

Current HLS systems typically provide very simple FPGA-side memory subsystems and little support for I/O outside of shared memory. This is due, in large part, to the complexity of building more flexible, application-specific environments. In addition to the topics below, we will discuss the value of library-based cache construction and describe the interfaces through which HLS-generated kernels are supported by LEAP-generated, application-specific, memory hierarchies.

The LEAP environment is open source (BSD license). Though the LEAP operating system is written in Bluespec System Verilog, user code may be written in any synthesizable language.

This half-day tutorial will cover:

  • Building algorithms using latency-insensitive design.
  • Passing messages through LEAP named connections.
  • Replacing block-RAM with LEAP memory services (cached virtual memory, optional cross-FPGA coherent caches).
  • Connecting to host files using LEAP STDIO.
  • Debugging applications using automatically generated, formatted state dumps.
  • Connecting HLS-generated kernels to LEAP-generated, application-specific, complex cache hierarchies.
  • Installing a virtual machine and walking through compiling a sample application.



Michael Adler is a member of the Technology Pathfinding and Innovation (TPI) group at Intel. After beginning his career on compiler back ends he has moved down the hierarchy toward processor simulation and microarchitecture research. His research is focused on the challenges of rapid specification of complex reconfigurable systems.

Kermin Elliott Fleming is a member of the Technology Pathfinding and Innovation (TPI) group at Intel. Elliott’s work is focused mainly on tools and techniques for implementing high-performance reconfigurable systems and architectures.

Hsin-Jung Yang is a doctoral candidate in the Department of Electrical Engineering and Computer Science at MIT. She received a B.S. from National Taiwan University and an S.M. from MIT. Her research interests include high-performance architectural design for reconfigurable computing.

Felix Winterstein is a doctoral candidate at Imperial College London. His research interests are high-performance computing using reconfigurable logic and high-level synthesis with an emphasis on compiler-based memory optimizations.