Tutorial FPL2014

Michael Adler edited this page May 21, 2015 · 1 revision

Tutorial FPL2014

The LEAP FPGA Operating System

We call computers “general purpose” in part because of standardization of software APIs. Device-specific code is wrapped by operating systems in abstract interfaces. Complex virtual memory hierarchies are exposed to programs through simple load/store interfaces. Programs are portable across hardware and, to some extent, across operating systems. The LEAP operating environment for FPGAs provides composable components and services for algorithms spanning one or more FPGAs and for hybrid algorithms combining FPGAs and software. LEAP APIs remain consistent across a variety of platforms, enabling application portability.

Historically, FPGA developers have concentrated on logic prototyping, verification, and embedded applications. As a result, there has been little motivation for interface standardization. FPGA vendors provide libraries of device drivers, though interfaces often change from device to device. Each development project typically debugs and rewrites interfaces when switching code from one hardware platform to another.

Recently, FPGAs have become more popular for algorithmic acceleration, with one or more FPGAs attached via high speed connections to a general purpose computer. Just as language and operating system research led to advances that allowed users to focus on applications instead of device details, FPGA users are coming to recognize the value of high level systems that reduce development time and simplify the mapping of complex algorithms.

In order to enable portability, all LEAP interfaces are latency-insensitive (LI). LI interfaces enable services that are composed of complex modules. For example, an application using LEAPœôòùs block-RAM interface can easily switch to LEAP Scratchpads: a cached memory hierarchy with storage backed in host virtual memory. LEAPœôòùs fundamental communication structure, the named channel, is also latency-insensitive. Because named channels are LI, LEAP is capable of routing channels automatically within a single FPGA, between multiple FPGAs and between FPGAs and software.

The LEAP environment is open source (BSD license). Though the LEAP operating system is written in Bluespec System Verilog, user code may be in any synthesizable language.

In the tutorial we will contrast LEAP with other FPGA environments, such as OpenCL. Attendees will leave with an understanding of latency-insensitive design, communication abstractions for multi-FPGA and hybrid algorithms, and LEAP memory models.

This half-day tutorial will cover:

  • Building algorithms using latency-insensitive design.
  • Passing messages through LEAP named connections.
  • Creating hybrid hardware/software applications.
  • Scaling applications to many FPGAs.
  • Replacing block-RAM with LEAP memory services (cached virtual memory, optional cross-FPGA coherent caches).
  • Connecting to host files using LEAP STDIO.
  • Debugging applications using automatically generated, formatted state dumps.
  • Managing builds and composing applications from component modules.
  • Example applications.


  • Michael Adler is a member of the Versatile System and Simulators Advanced Development (VSSAD) group at Intel. After beginning his career on compiler back ends he has moved down the hierarchy toward processor simulation and microarchitecture research. His research is focused on the challenges of detailed performance analysis of large systems.
  • Kermin Elliott Fleming has a B.S. and M.S. from Carnegie Mellon University and a PhD in Computer Science from MIT. Elliott’s work is focused mainly on tools and techniques for implementing high-performance reconfigurable systems, with an emphasis on wireless transceivers.
  • Hsin-Jung Yang is a doctoral candidate in the Department of Electrical Engineering and Computer Science at MIT. She received a B.S. from National Taiwan University and an S.M. from MIT. Her research interests include high-performance architectural design for reconfigurable computing.
  • Joel Emer is an Intel Fellow and director of microarchitecture research at Intel where he leads the VSSAD group. In his spare time, he is a professor of the practice at MIT, where he teaches and supervises student research. His current research interests include performance modeling frameworks, reconfigurable logic computing, parallel and multithreaded processors, cache organization, and processor pipeline organization. He received a PhD in electrical engineering from the University of Illinois. He is an ACM Fellow and a Fellow of the IEEE, and was the 2009 recipient of the Eckert-Mauchly award.
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