PicoStack v0.2.0 — one board, one Pico

PicoStack v0.2.0 — one board, one Pico

v1 needed two boards for the smallest possible system: a base board (Pico
seat, 24 V input, 5 V regulator) plus a module. v2 abolishes the base
board. One module plus a Raspberry Pi Pico is now a working device.

What changed

• Pico-native stacking geometry. Every module carries two 1×20 socket
  rows, 17.78 mm apart on a 2.54 mm grid — the Pico's own pinout, not an
  arbitrary 2×20 block. The Pico plugs straight into the top of the stack
  and all 40 pins run down through it. Not a single pin's role changed
  from v1 — only the connector geometry.
• A supply cell on every board. 3.5 mm screw terminal (6–30 V),
  reverse-polarity protection, TVS, a K7805-1000R3 regulator and a
  Schottky diode into VSYS. Any number of fed boards can coexist in one
  stack; one is enough to power the whole chain.
• Every spare GPIO, broken out. The 18 free Pico GPIOs plus several
  3V3/GND pads come out as labelled solder pads on the board edge, on the
  bottom copper layer so the rotation-safety keep-out stays intact.
• Boards grew from 64 × 60 mm to 75 × 65 mm — one size for every
  module, to fit the second stacking row, the supply cell and the edge
  pads. M3 pattern and rotation landing points scale with it; the mating
  rule is unchanged.
• The connector-vs-contract probe actually runs now. It used to crash
  silently on every v2 board and could never turn red; it's fixed and now
  measures the built board for real.

Four defects found and fixed (none caught by ERC or DRC)

The v2 rewrite re-examined every v1 circuit and found four real defects
that had already passed KiCad's electrical and design-rule checks:

1. A fail-unsafe emergency-stop gate. The e-stop driver was an
   inverting buffer (SN74LVC1G06): an intact loop blocked the motor
   and a broken wire released it — exactly backwards for a safety
   circuit. Replaced with the pin-identical, non-inverting SN74LVC1G07.
2. A reverse-polarity FET wired to crowbar instead of block. The
   protection FET's drain sat on the local supply rail instead of the
   input, so reverse voltage turned its body diode and the TVS into a
   short circuit rather than an open one.
3. A VSYS pin the contract itself forbids. An early draft of the new
   supply cell used a pin the contract's NICHT_BELEGBAR list had already
   ruled out — it would have fed nothing.
4. A shared placement scaffold hard-wiring motor signals onto every
   module. Code copied from the motor board silently routed motor-only
   nets onto the dimmer boards too, costing them two hardware PWM
   channels before anyone noticed.

Each of these now has a dedicated probe with a red proof: a test that
demonstrably fails when the defect is reintroduced.

Board family in this release

Board	Size	State
Motor module	75 × 65 mm	routed, DRC-clean
Dimmer1 (1 channel)	75 × 65 mm	routed, DRC-clean
Dimmer3 (3 channels)	75 × 65 mm	routed, DRC-clean
Dimmer4 (4 channels)	75 × 65 mm	routed, DRC-clean

The v1 base board (hardware/kicad/sockel/) is not part of this
release — it stays archived at
v0.1.0 and is
marked v1-only throughout the repository.

Assets

Gerbers + JLC-format BOM/CPL/placement, ready to upload to JLCPCB, for
all four boards. See
hardware/fertigung/ORDERING.md
for the ordering walkthrough, including three traps that already cost
real money in v1.

Tests

python3 tests/run_all.py: 13 suites, all green.

Open item

The load-bearing assumption of the whole flashing scheme — that a Pico
can write a module MCU over its ROM bootloader — is still not verified
on real hardware (no STM32C011 on the bench yet). Status and next steps:
docs/nachweis-2026-08.md.