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Nakazoto edited this page Jun 29, 2022 · 6 revisions

Full Adder 1713038B

The Full Adder is a very interesting design. At its heart it's a look-ahead fast carry adder with 42-stages. Being a discrete transistor design, the Bendix G-20 takes a certain amount of time to stabilize, particularly the N and D registers. Additionally, with 42-stages in the Full Adder chain, the amount of time it takes for the carry to propagate down the line is considerable. To alleviate this, the full adder chain uses certain lines in each step to enact on stages later in the line, essentially predicting what the carry will be and greatly increasing speed.

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Schematic

This schematic was reverse engineered by tracing out each individual line on the board itself. We are fairly confident it is mostly correct, but there could be errors still present.

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Design

There are a few very interesting design choices going on here. Most notably is the fast carry feature. Bendix utilizes a Propagate Carry and Propagate Kill feature to either generate or kill a carry. The exact method of their use of these two signals is quite in-depth and covered in much greater detail in the service manual available on bitsavers at this link. Here is the design of a typical adder circuit:

And here is the design of the typical leapfrog circuit:

However, the Full Adder board that we have here doesn't include any of the leapfrog carry kill circuitry, that is all offloaded to other portions of the machine. This Full Adder board is simply just a single 1-bit Full Adder with two operands and a carry in providing a sum and a carry out. There are two unique things to note here however.

  1. The Full Adder is built using essentially a multiplexer lookup table, similar to using a ROM to replace a collection of logic.
  2. There are six inputs, two inputs for each operand (A, B or Carry). Each operand input uses the operand and inverse operand. There are four outputs for sum and carry. Each gives the output and its inverse.
  3. In the logic diagram below I included three inverters to represent the inverse of each operand. These inverters are not included on the actual board. They operand and it's inverse are supplied by the registers or the propagate carry.

Here is the Logisim file for download.

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