Full Adder
The Full Adder is a very interesting design. At its heart it's a look-ahead fast carry adder with 42-stages. Being a discrete transistor design, the Bendix G-20 takes a certain amount of time to stabilize, particularly the N and D registers. Additionally, with 42-stages in the Full Adder chain, the amount of time it takes for the carry to propagate down the line is considerable. To alleviate this, the full adder chain uses certain lines in each step to enact on stages later in the line, essentially predicting what the carry will be and greatly increasing speed.
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This schematic was reverse engineered by tracing out each individual line on the board itself. We are fairly confident it is mostly correct, but there could be errors still present.
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There are a few very interesting design choices going on here. Most notably is the fast carry feature. Bendix utilizes a Propagate Carry and Propagate Kill feature to either generate or kill a carry. The exact method of their use of these two signals is quite in-depth and covered in much greater detail in the service manual available on bitsavers at this link. Here is the design of a typical adder circuit:
And here is the design of the typical leapfrog circuit:
However, the way in which the Full Adder is implemented on the physical chip itself is very, very different, as can be seen by the schematic above. I have tried to recreate the schematic to the best of my ability in Logisim. However, depending on whether this uses Positive Logic or Negative Logic changes the design slightly.
As you can see, it bears very little resemblance topographically to the typical adder stage shown above. However, I believe that this is closer to a multiplexer with various inputs and outputs to essentially recreate the logic of the Full Adder, similar to a ROM lookup table. However, I have yet to get this logic design functioning correctly.