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v0.3.0 — Minimal machine + hardware IRQ delivery

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@PandaCatz PandaCatz released this 13 Jul 20:25
v0.3.0
c437b82

Minimal machine + hardware IRQ delivery.

A minimal core-ws::Machine wires the V30MZ to memory, the I/O ports, and the 8-line interrupt controller, delivering the highest-priority enabled hardware IRQ before each instruction (and waking a halted CPU). Relocatable IVT base (REG_INT_BASE), edge/level semantics, and no auto-ack — the ISR must write REG_INT_ACK ($B6), matching hardware.

111 tests. The memory map is still a placeholder flat 1 MiB — the real WonderSwan map is later work.

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