v0.7.0 — Real memory map (boots from cartridge ROM)

Real WonderSwan memory map — the machine boots from cartridge ROM.

Replaces the placeholder flat 1 MiB bus with core-ws::memory::MemoryMap, routing the physical address space per the verified spec (docs/hardware/01-cpu-v30mz.md):

• Internal RAM sized by model (16 KiB mono / 64 KiB colour), with the mono 0x04000+ hole left as an explicit open question rather than a fabricated mirror.
• Cartridge ROM bank windows — $C0 linear (masked to the mapper's width), $C2/$C3 ROM0/ROM1 — and the $C1 SRAM window, all driven off the decoded CartHeader (bus width, save/ROM sizing, mapper).
• I/O three-way decode ($B8–$BF EEPROM, $C0–$FF cartridge bus, SoC low-9-bit alias, else open bus) with model-dependent open-bus reads ($90 mono / $00 colour).
• $A0 system control — one-way boot-ROM lockout latch, colour status, and the ROM bus width seeded from the cartridge footer (community bug #9 flowing through to the runtime register).

Machine::with_cartridge now boots: reset FFFF:0000 → the linear window → the cartridge footer's boot far-jump → executing from ROM (test boots_from_cartridge_rom_via_the_reset_vector).

An adversarial review caught a boot-blocking bug before merge — $C0 powered up to 0, so the reset vector only reached the footer on ROMs ≤ 1 MiB; fixed to $FF and locked with a multi-size test (incl. 4 MiB). 153 tests pass in debug and release; CI green.

Deferred as explicit gaps: wiring the fixed subsystems to the I/O dispatch, the boot-ROM overlay, the EEPROM/RTC protocols, DMA, PPU rendering, and timing. Still not a playable emulator.

v0.6.0 — Cartridge footer decode (bug #9)

Cartridge footer decode — community-bug ledger fully triaged.

format-ws now decodes the 16-byte cartridge footer into a typed CartHeader: publisher, system (WS/WSC), game id, version, ROM-size and save-type code tables, flags (orientation + bus width), mapper/RTC, the boot far-jump, and the checksum. Undocumented codes decode to explicit Other/Unknown/None — never guessed.

• Fixes community bug #9 (8-bit ROM bus). Footer flags byte (0x0C) bit 2 gives BusWidth::{Eight,Sixteen}, surfaced by WsCartridge::bus_width. Hardcoding a 16-bit bus corrupts reads on the Pocket Challenge V2 and early carts.
• Layout adversarially verified against WSMan, the WSdev wiki, ares, and Mednafen (5 source finders → reconcile → 6 adversarial verifiers). The pass fixed the bus-width bit to bit 2 (0=8/1=16, over WSMan's contradictory cart-table reading) and corrected save-code 0x01 to 32 KiB. Citations, resolved disputes, and open gaps: docs/hardware/06-cartridge.md.
• Promotes the provisional checksum to verified; ws-cli --rom prints the decoded header (derived facts only, no ROM bytes).

Community-bug ledger: 6 fixed · 3 partial · 0 pending (the partials #1/#7 are blocked on the unresolved cycle-unit question). 142 tests pass in debug and release; CI green.

Honest scope: still not a playable emulator. The next piece is the real WonderSwan memory map, which wires the fixed subsystems to their registers and consumes this decoded header.

v0.5.0 — Community-bug fixes (6 subsystems, audited)

Community-bug fixes — six subsystems, adversarially audited.

Isolated, unit-tested fixes for the recurring WonderSwan emulation bugs catalogued in docs/COMMUNITY-BUGS.md, each with a named test pinning the behaviour existing emulators get wrong. All were adversarially audited against WSMan / WSdev / ares (the audit corrected several — see the ledger's Audit-corrected notes):

• #4 noise LFSR keeps running in wave mode (Clock Tower PRNG seed) — core-ws::apu
• #3 UART disable clears pending TX/RX IRQs (startup lockups) — core-ws::serial
• #8 internal EEPROM WS vs WSC size detection (1 Kbit / 16 Kbit) — core-ws::eeprom
• #5 monochrome palette pool indirection — core-ws::palette
• #6 color-zero transparency keyed on bit depth — core-ws::palette
• #2 sprite-DMA double-buffering near line 142 (tearing) — core-ws::ppu

Scorecard: 5 fixed · 3 partial · 1 remaining (of 9). 133 tests pass in debug and release.

Honest scope: these subsystems are isolated and tested but not yet wired to a register dispatch, and there is no memory map, PPU rendering, or timing yet — this is not a playable emulator.

v0.4.0 — V30MZ validated against the V20 oracle

V30MZ validated against the V20 single-step hardware oracle.

cpu-v30mz was run against the V20 single-step oracle over ~620k runnable cases: 93.49% exact, zero defined-behaviour bugs — every divergence is a V20-only instruction or an officially-undefined flag, not a bug in the documented behaviour.

The run found and fixed the Flags::to_word high-bits bug, which also resolved the MD-bit open question (→ 0xF002). See docs/VALIDATION.md.

v0.3.0 — Minimal machine + hardware IRQ delivery

Minimal machine + hardware IRQ delivery.

A minimal core-ws::Machine wires the V30MZ to memory, the I/O ports, and the 8-line interrupt controller, delivering the highest-priority enabled hardware IRQ before each instruction (and waking a halted CPU). Relocatable IVT base (REG_INT_BASE), edge/level semantics, and no auto-ack — the ISR must write REG_INT_ACK ($B6), matching hardware.

111 tests. The memory map is still a placeholder flat 1 MiB — the real WonderSwan map is later work.

v0.2.0 — V30MZ instruction set complete

V30MZ instruction set complete.

The NEC V30MZ core (80186-compatible plus the undocumented SALC, without the V20/V30 REP extensions) executes the full documented 8086/80186 instruction set: ALU + GRP1/GRP3, MOV/XCHG/LEA, INC/DEC, TEST, CBW/CWD, MUL/IMUL/DIV/IDIV, GRP2 shifts/rotates, GRP4/5 indirect CALL/JMP/PUSH, stack ops, string ops + REP, control flow, IN/OUT, and INT/INTO/IRET with the interrupt-delivery sequence.

Register file, flags, 20-bit segmented addressing, CS:IP = FFFF:0000 reset, and full ModR/M decode. 108 tests.

Cycle-accurate timing is deliberately deferred until the master-vs-CPU cycle-unit question is measured.

v0.1.0 — Phase 1: headless skeleton

Phase 1 — headless skeleton.

Establishes the accuracy-first workspace: deterministic contracts (integer emulated time, typed video/audio/input packets, the Core/OutputSink traits, non-panicking errors), a defensive borrowed .ws / .wsc parser (structural validation, hostile-input handling), a synthetic core + capture sink with stable FNV-64 hashing, and a headless CLI.

Rust 1.96.0 pinned; unsafe forbidden workspace-wide; warnings are errors.

Scope: this proves the shared contract and the headless capture path only — it is not console emulation.