Skip to content

ARM NVIDIA Port

André Borchert edited this page Jun 13, 2026 · 3 revisions

ARM NVIDIA Port

Purpose

This page defines the fourth platform target for OSAI: ARM/NVIDIA N1X-compatible and GB10-class systems.

Contents

Why ARM/NVIDIA Last

ARM/NVIDIA comes after x86 QEMU, Intel Desktop, and Intel Xeon because it needs a stable OS architecture before platform-specific AArch64 work. The goal remains CPU-only AI, not CUDA or GPU dependency.

Platform Assumptions

Target assumptions:

  • AArch64;
  • UEFI/SBSA where available;
  • Device Tree fallback later;
  • GIC interrupt controller;
  • SMMU for DMA protection;
  • LPDDR or unified memory behavior;
  • mixed core or cluster topology.

Boot and Interrupts

The first ARM path should prefer UEFI plus ACPI/SBSA where possible. GIC support and timer support are required before meaningful service work.

Memory Behavior

LPDDR/unified memory systems need explicit bandwidth measurement. Shared model weights, prefaulted arenas, and no-swap AI memory remain required.

Core Policy

Default policy:

  • highest-performance cores: AI inference;
  • middle cores: network and tokenizer workers;
  • efficiency cores: SSH, logging, Git, source indexing, build/test;
  • cluster migration forbidden for hot AI workers.

Success Criteria

OSAI boots, runs AI Cell lifecycle tests, keeps hot workers on intended cores, and reports platform-specific memory and latency counters.

Clone this wiki locally