Glossary

Glossary

Purpose

This page defines common XAI OS terms.

Terms

XAI OS: A design-stage server OS for CPU-only embedded AI app agents.

AI Cell: A fixed-resource execution unit that owns cores, memory arenas, NIC queues, model mappings, source indexes, workspaces, and telemetry counters.

CPU-only AI: AI inference and agent work that does not require CUDA, Metal, GPU, or vendor accelerator runtimes.

Embedded app agent: An application-local AI agent with scoped access to source code, build/test commands, Git worktrees, and deployment hooks.

Hot path: The latency-sensitive path from request arrival through agent inference and response.

Control plane: Slow management work such as SSH, service startup, logging, updates, Git orchestration, and supervision.

Model arena: Memory region holding model weights, preferably shared read-only and mapped with large pages where possible.

KV/cache arena: Private per-agent memory for inference state.

Shared weights: One physical model-weight copy mapped read-only into multiple AI Cells.

Core lease: Exclusive assignment of a CPU core to a cell or worker role.

Scheduler jitter: Timing variation introduced by scheduling, migration, interrupts, or unrelated OS work.

NUMA: Non-uniform memory access; memory locality matters across sockets or nodes.

QEMU: Emulator used for early XAI OS bring-up on macOS.

UEFI: Firmware interface used for booting XAI OS.

VirtIO: Paravirtual device model used for QEMU storage and networking.

NIC queue: Hardware or virtual network RX/TX queue.

IOMMU: I/O memory management unit for DMA protection on many x86 systems.

SMMU: ARM system memory management unit for DMA protection.

AMX: Intel matrix extension family that may accelerate some CPU-only AI kernels when available, always behind feature detection and fallback.

P-core: Intel performance core, preferred for hot inference and low-latency network work on Intel Desktop.

E-core: Intel efficiency core, preferred for housekeeping, logging, source indexing, Git, and build/test work where available.

Design target: A performance goal that must not be treated as measured proof until benchmarked against a tuned Linux/BSD baseline.

Tuned Linux/BSD baseline: A serious comparison configuration using CPU affinity, isolated cores, hugepages, IRQ affinity, NUMA policy, performance governor, and kernel-bypass networking where relevant.

Related Pages

• Performance Targets
• Architecture
• AI Cells