Intel Xeon Port

Intel Xeon Port

Purpose

This page defines the third platform target for XAI OS.

Contents

• Why Xeon Third
• NUMA Policy
• CPU Feature Policy
• Many AI Cells
• Benchmark Focus
• Success Criteria

Why Xeon Third

Intel Xeon is the serious multi-agent server target. It introduces NUMA, many memory channels, server NICs, MSI-X, IOMMU, multi-queue NVMe, and many concurrent AI Cells.

NUMA Policy

Default policy:

• one latency-sensitive AI Cell stays inside one NUMA node;
• model weights are NUMA-local or deliberately replicated;
• NIC and NVMe queues are NUMA-local when possible;
• cross-node memory is forbidden unless explicitly configured.

CPU Feature Policy

Vector and AMX-style features may be used only behind detection and with generic fallbacks.

Many AI Cells

The Xeon port must prove admission control for memory bandwidth, queues, cores, and build/test pressure across many agents.

Benchmark Focus

Measure p99/p999 latency under concurrent AI, Git, and build/test load. Track memory bandwidth, migration, context switches, page faults, and NUMA locality.

Success Criteria

Multiple AI Cells run predictably with no hot-path migration, no post-warmup hot-path page faults, and documented latency/memory results against tuned baselines.

Concrete acceptance gates:

• AI Cell is confined to one NUMA node unless explicitly configured otherwise;
• model weights are NUMA-local or intentionally replicated;
• NIC queue and NVMe queue locality are reported;
• multi-cell admission control rejects unsafe oversubscription;
• AMX/vector worker policy is documented where hardware supports it;
• benchmark artifacts compare against tuned Linux/BSD.

Related Pages

• Memory System
• Scheduler and Core Isolation
• Benchmark Result Format