FPGA bitstreams - September 2026 (MEGA65 + MiSTer)

ND-120 FPGA — Release 2 (bitstreams-2026-09)

Ready-built bitstreams so you can run the 1988 Norsk Data ND-120 CPU without
installing Vivado, Gowin or Quartus. Attached to this GitHub Release; the
binaries are never checked into git.

Source commit: b09302e — mega65: the whole ND-120 machine on the
MiSTer2MEGA65 framework, both revisions.

What is new since Release 1 (bitstreams-2026-08):

• MEGA65 — the whole machine, first release, two cores (see below).
• MiSTer (DE10-Nano) — first release, TDV2200 console.
• QMTECH XC7A35T SDRAM core board — first release. The same Artix-7 die as
  the Digilent Basys3, but with 32 MB of SDRAM on board. That is what lifts the
  Basys3's 24 KB memory ceiling and makes this the one Artix-7 board of that
  size able to run SINTRAN III.
• The real TDV2200 box-drawing font (character set 2, dumped from
  RetroCore), now embedded in font_rom.v so every board carries the
  correct glyphs with no loose hex file to copy.
• The physical Left-arrow key fix (the Nexys USB-PS/2 bridge drops the E0
  prefix; Left arrives as bare 0x6B).
• A fourth power-on banner line: board / CPU clock / cache on-off, filled
  in from the build settings.

Console settings — every file, no exceptions: 115200 baud, 7 data bits,
EVEN parity, 1 stop bit, no flow control. One terminal setting for the whole
release.

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Artifacts

File	Board	Format	CPU clock	Verified
nd120_mega65_rev3_13MHz_115200.cor	MEGA65 R3 / R3A	.cor	13.33 MHz	Built + timing-clean. NOT yet run on a MEGA65.
nd120_mega65_r6_20MHz_115200.cor	MEGA65 R4 / R5 / R6	.cor	20 MHz	Built + timing-clean. NOT yet run on a MEGA65.
nd120_nexys4ddr_33MHz_115200.bit	Nexys 4 DDR	.bit	33.333 MHz	pending — refresh build in preparation
nd120_tang20k_fast20_20MHz_115200.fs	Tang Nano 20K	.fs	20.25 MHz	pending — refresh build in preparation
nd120_mister_20MHz_115200.rbf	MiSTer (DE10-Nano)	.rbf	20 MHz	Built + run on a DE10-Nano (02-SEP-2026): boots to OPCOM, boots SINTRAN from a mounted Winchester image, TDV2200 font and keyboard confirmed.
nd120_qmtech_a35t_20MHz_115200.bit	QMTECH XC7A35T SDRAM core board	.bit	20 MHz	Built + timing met (+4.645 ns). NOT yet run on a board.
SHA256SUMS	—	—	—	checksums of the four attached files

The two MEGA65 cores, the QMTECH .bit and the hardware-verified MiSTer
.rbf are attached; the Nexys/Tang refresh is added as each is built and
checked, and the combined SHA256SUMS is regenerated at that point.

SHA-256 (all four attached files)

a24dee1a5c2503286013d29738a3629436da2aa74559ddecaf45002e56abb2a0  nd120_mega65_rev3_13MHz_115200.cor
c00b13faf3a8ffec4a67a200e8bc8128ef8ed85d415002746f23d595b086caa3  nd120_mega65_r6_20MHz_115200.cor
deb9e1ea499baa0dab8d6595f01f696a360b4df536209d9d42b0397df680520a  nd120_mister_20MHz_115200.rbf
61d23600cf20de9f0754085399b3f15579a6ac931fb5cfc35f334d675f204732  nd120_qmtech_a35t_20MHz_115200.bit

Both MEGA65 cores were replaced on 05-SEP-2026. If you downloaded a
.cor before that date you have the 02-SEP build, and its checksum
(e936a868... for R3, 28f7d186... for R6) will not match the block
above - that is the old file, not a corrupt download. Download again to
get the current core. The MiSTer .rbf is unchanged and its checksum is
the same as it always was.

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MEGA65 — read this first

These two cores are built and timing-clean, but no MEGA65 was available to
run them on. You are the verification channel. They go out labelled
"not yet run on a MEGA65". QUICKSTART-mega65.md tells you what to see and what
to report back.

Pick the core for your board revision — the flash menu refuses a
wrong-model .cor:

• R3 / R3A → nd120_mega65_rev3_13MHz_115200.cor (13.33 MHz). The 4 MB of
  ND-120 memory lives in the board's HyperRAM (Nexys cache seam + an Avalon
  port). Timing: WNS +0.093 ns, WHS +0.032 ns.
• R4 / R5 / R6 → nd120_mega65_r6_20MHz_115200.cor (20 MHz). The 4 MB lives
  in the board's 64 MB SDRAM (the MiSTer sheet-49 bridge). Timing:
  WNS +0.249 ns, WHS +0.002 ns. Built for R6; R4/R5 rebuild from source with
  BOARD=r4 / BOARD=r5 (same memory, different top).

Both cores are the whole machine: CPU, 4 MB memory, TDV2200 console on the
MEGA65's own keyboard and screen, and the framework's virtual floppy 0/1 +
Winchester 0/1 + tape.

Rebuilt 04-SEP-2026 (uploaded here 05-SEP): the cores now carry the RAW
microcode word 0o2002 as the real PROM holds it - boards get the raw word,
simulators get the 2024 patched one - and the MEGA65's RUN/STOP key is now
the ND-120 EXIT (SLUTT) key. Build stamps 3e1f90c+ 04-Sep-2026 09:46 (R3)
and bc612ad+ 04-Sep-2026 09:25 (R6); the same stamp shows in the on-screen
banner and in the .cor header, so you can tell which build you are running
without checksumming it.

What to report: does the power-on banner render (including the box-drawing
lines), does the Left arrow work, does OPCOM answer, does 20500& run — and the
power LED verdict. Details in QUICKSTART-mega65.md.

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QMTECH XC7A35T — read this first too

Also built and timing-clean, also never run on a board. Same honesty as
the MEGA65 cores above — but this one asks more of you, because the board is a
bare FPGA module rather than a finished product.

It has no USB data path (the Mini USB socket is power only), no on-board
UART and no SD slot. So the console and the SD card go on jumper wires to
a raw 2x25 header, and programming is JTAG only and volatile: a power
cycle wipes the FPGA and you program it again. You need a Xilinx Platform
Cable USB II, a 3.3 V USB-serial adapter, and a Digilent Pmod MicroSD or
Pmod SD.

It is worth the trouble because of what it is: the same Artix-7 die as the
Basys3, which cannot run SINTRAN for want of memory — and no clock speed fixes
that. This board carries the whole machine at 20 MHz with +4.645 ns of timing
margin: CPU, 4 MB of main memory in the on-board SDRAM, SD-card storage and
the serial console, in 12,619 of 20,800 logic cells and 22 of 50 block RAM
tiles.

One fact in the wiring guide is unmeasured, and you are the person who can
measure it: which pin of header JP3 is ground. The candidates are pins 3, 4,
21 and 22; the 6-pin JTAG header gives you a known ground to check them
against with a meter. Do that before wiring anything — a card with no shared
ground behaves exactly like a broken card, and pin 1 of that header is the
5 V rail.

What to report: does OPCOM answer when you press ENTER, does 20500&
reach SINTRAN, which JP3 pin turned out to be ground, and which of the two
LEDs lit. QUICKSTART-qmtech-a35t.md has the full pin table, a wiring
diagram, the meter check and the console settings.

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How to load them

• MEGA65 — .cor files flash from the MEGA65's own core menu; SD card holds
  the /nd120 disc images. Full walkthrough: QUICKSTART-mega65.md.

• Nexys 4 DDR — microSD config at power-on (one card carries the .bit and
  the disc image), or Vivado/openFPGALoader over USB-JTAG.
  See QUICKSTART-nexys4ddr.md.

• Tang Nano 20K — openFPGALoader -f writes onboard SPI flash once, boots
  the ND-120 at every power-on after. See QUICKSTART-tang-nano-20k.md.

• MiSTer (DE10-Nano) — copy nd120_mister_20MHz_115200.rbf to the SD card
  as /media/fat/_Computer/ND120.rbf and load it from the MiSTer menu. Attach
  a Winchester image (for example WD0.IMG) from the OSD, then at the #
  monitor type & to boot it. The console is the MiSTer's own screen and
  keyboard; the CPU's serial line is also on the HPS /dev/ttyS1 at 115200 7E1.
  Full walkthrough: QUICKSTART-mister.md.

• QMTECH XC7A35T — no copy-a-file path exists on this board. Wire the
  console and an SD Pmod to header JP3 first, then program
  nd120_qmtech_a35t_20MHz_115200.bit over the 6-pin JTAG header with a
  Xilinx Platform Cable USB II — Vivado, or the free Vivado Lab Tools, is
  enough. Volatile: re-program after every power cycle. Wiring diagram and
  walkthrough: QUICKSTART-qmtech-a35t.md.

Disc image is not in the release (instructions only): the machine needs a
Winchester image on the card's FAT root. A bitstream with no image still comes
up in OPCOM — the quickstarts use that as the "it works" smoke test.

FPGA bitstreams - August 2026 (SINTRAN III on Nexys 4 DDR and Tang Nano 20K)

Ready-built FPGA bitstreams for the ND-120 recreation - flash and run, no FPGA toolchain needed.

Every file runs the console at 115200 baud, 7 data bits, EVEN parity, 1 stop bit (picocom -b 115200 -y e -d 7 -p 1 <port>).

File	Board	CPU clock	Status
nd120_nexys4ddr_45MHz_115200.bit	Digilent Nexys 4 DDR	45.45 MHz	boots SINTRAN III, silicon-verified
nd120_nexys4ddr_16MHz_115200.bit	Digilent Nexys 4 DDR	16.667 MHz	safe build, large timing margin (STA-clean; the 16.667 MHz configuration is the one with 7/7 validated boot cycles)
nd120_tang20k_fast20_20MHz_115200.fs	Sipeed Tang Nano 20K	20.25 MHz	boots SINTRAN III, silicon-verified, timing-clean
nd120_tang20k_slow_6.75MHz_115200.fs	Sipeed Tang Nano 20K	6.75 MHz	safe build at the long-validated speed (STA-clean)
SHA256SUMS	-	-	checksums of the four files above

How to load them - step-by-step guides:

• Nexys 4 DDR: QUICKSTART-nexys4ddr.md - including the hardware-verified no-software path: copy the .bit + disc image to a FAT32 microSD, set jumpers JP1 (pins 3-4, "USB/SD") and JP2 (SD side), power on.
• Tang Nano 20K: QUICKSTART-tang-nano-20k.md - one openFPGALoader -f command flashes the board permanently.

Disc image: booting SINTRAN III needs a Winchester disc image on the microSD (FAT32, root directory). The image is not distributed here - it contains SINTRAN III, which is not this project's to license. The quickstarts explain what is needed; without an image the machine still answers on its OPCOM console (the smoke test).

Timing background: the frequency search and per-board bottleneck analysis behind these clocks is in timing.md and the device comparison.

Source commits: Tang .fs files built at 798e547; Nexys .bit files rebuilt 27-AUG at the fix-sd-card merge (tag now points at bea2fb8, whose RTL is what the current Nexys files were built from).

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Updated 27-AUG-2026: both Nexys 4 DDR bitstreams replaced with builds
carrying the SD slot power-cycle fix (commit on branch fix-sd-card,
merged to main). With these, the SD-card deployment path works END TO END:
the board configures itself from the microSD and boots SINTRAN from the
same card - no PC software at all (see QUICKSTART-nexys4ddr.md, Path 2).
The original 26-AUG Nexys files configured from SD but could not boot
discs afterwards (the card was left in the config controller's SPI mode;
the design now power-cycles the slot at configuration, reset and master
clear). The 45 MHz file is silicon-verified three ways: JTAG boot,
MACL-then-boot, and SD-config-then-boot. Tang files are unchanged (the
Tang does not configure from SD). SHA256SUMS regenerated.