FPGA bitstreams - August 2026 (SINTRAN III on Nexys 4 DDR and Tang Nano 20K)

Ready-built FPGA bitstreams for the ND-120 recreation - flash and run, no FPGA toolchain needed.

Every file runs the console at 115200 baud, 7 data bits, EVEN parity, 1 stop bit (picocom -b 115200 -y e -d 7 -p 1 <port>).

File	Board	CPU clock	Status
nd120_nexys4ddr_45MHz_115200.bit	Digilent Nexys 4 DDR	45.45 MHz	boots SINTRAN III, silicon-verified
nd120_nexys4ddr_16MHz_115200.bit	Digilent Nexys 4 DDR	16.667 MHz	safe build, large timing margin (STA-clean; the 16.667 MHz configuration is the one with 7/7 validated boot cycles)
nd120_tang20k_fast20_20MHz_115200.fs	Sipeed Tang Nano 20K	20.25 MHz	boots SINTRAN III, silicon-verified, timing-clean
nd120_tang20k_slow_6.75MHz_115200.fs	Sipeed Tang Nano 20K	6.75 MHz	safe build at the long-validated speed (STA-clean)
SHA256SUMS	-	-	checksums of the four files above

How to load them - step-by-step guides:

• Nexys 4 DDR: QUICKSTART-nexys4ddr.md - including the hardware-verified no-software path: copy the .bit + disc image to a FAT32 microSD, set jumpers JP1 (pins 3-4, "USB/SD") and JP2 (SD side), power on.
• Tang Nano 20K: QUICKSTART-tang-nano-20k.md - one openFPGALoader -f command flashes the board permanently.

Disc image: booting SINTRAN III needs a Winchester disc image on the microSD (FAT32, root directory). The image is not distributed here - it contains SINTRAN III, which is not this project's to license. The quickstarts explain what is needed; without an image the machine still answers on its OPCOM console (the smoke test).

Timing background: the frequency search and per-board bottleneck analysis behind these clocks is in timing.md and the device comparison.

Source commits: Tang .fs files built at 798e547; Nexys .bit files rebuilt 27-AUG at the fix-sd-card merge (tag now points at bea2fb8, whose RTL is what the current Nexys files were built from).

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Updated 27-AUG-2026: both Nexys 4 DDR bitstreams replaced with builds
carrying the SD slot power-cycle fix (commit on branch fix-sd-card,
merged to main). With these, the SD-card deployment path works END TO END:
the board configures itself from the microSD and boots SINTRAN from the
same card - no PC software at all (see QUICKSTART-nexys4ddr.md, Path 2).
The original 26-AUG Nexys files configured from SD but could not boot
discs afterwards (the card was left in the config controller's SPI mode;
the design now power-cycles the slot at configuration, reset and master
clear). The 45 MHz file is silicon-verified three ways: JTAG boot,
MACL-then-boot, and SD-config-then-boot. Tang files are unchanged (the
Tang does not configure from SD). SHA256SUMS regenerated.