DCDCv9-3r1.3

Important update for all v9-3r users!

Edit: The issue described in this release was due to inproper setting of the minimum switching frequency. It has been fixed in the build guide on July 18, 2025 without any new release.

An issue with Q11 was found. The exact cause of it's failure is still not fully understood.
Here what's currently known:

• Q11 became permantently conductive when the DCDC operated at above 570V from a HV battery during enabling or applying load
• this failure appeared 2 times on the same DCDC within 3 Days at above 570V but never in the weeks before below 550V
• currently this failure cannot be reproduced with a HV power supply and has not appeared during tests, not even at 605V
• new measurements show, that at 600V input a slight overvoltage between Q11's Drain-Source appear on the rising edge, resulting in 620V seen by the FET. Although the FET is rated for 650V, it is arguably not optimal.
• starting at around 575 V the U_ds rise and fall times drastically increased from 30 ns (575V) to around 60 ns (600V) on Q11 and Q10
  
  Q10 Mesurement, Yellow: Drain-Source Voltage, Purple: Gate-Source Voltage
• Gate Drive Voltage remains the same
• Previous version (v9-2) operates mostly on the same halfbridge design, but 10 Ohm gate resistors instead of 4.7 Ohm. The resonant circuit is also a bit different. The v9-2 was used as a temporary replacement for v9-3 and did not suffer any failures under similar conditions
• this issue did not occur to another teams's v9-3 replica (yet?)

Suspected cause (best guesses)

Gate Resistors
At first the lower value gate resistors where suspected to cause higher overvoltage due to faster switching. However measurements show, that it only slightly influcences the overvoltage at lower voltages. At 600V input the Drain-Source voltage was 616V at 10 Ohm compared to 619V at 4.7 Ohm. So this might be not the cause.

Dead-Time
The weird increase of rise- and fall times above 575V raised the question, whether the dead time was too short. The current dead time was measured at 113 ns (between the outputs of the UCC25600). Increasing it to 180 ns did nothing but increase the current consumption by ~0.3 mA at 500 V (no load). The wave forms and rise/fall times remained the same. The waveforms also did not hint (afaik) to anything that could resemble a halfbidge short due to too low dead time.

Q10 Mesurement, Yellow: Drain-Source Voltage, Red: Drain-Souce Current measured with a rogowski coil (might be not very accurate, just a test)

Hard switching
Although the LLC topology is known for it's soft switching, this is not entirely true depending on input voltage and load.
The primary current waveform transitions with higher input voltage and lower load from a sine to a triangle. This means, that the FETs are switching while current is still conducted, thus being hard switched. This might put load on the FETs while switching, which may result in longer switching times (not sure about this) and higher losses. However, higher losses have not been thermally measured.
Also when enabled, the softstart will begin switching at around 350 kHz. This can also cause hard switching at enable or self restart (e.g. due to overload) → Might be a main cause.

All of the above
As the pieces come together, it could be the following picture:
During turn on, the softstart will operate at higher frquencies, causing hard switching and prolonged switching times. The dead time might then be too short, causing a half bridge short (but why only Highside FET damaged?). It is also possible, that the smaller value on the gate resistors are causing the FETs to be switched even harder, causing more thermal stress/EMI/overvoltage. This might be also an issue for the Bootstrap (Diode) - however UVLO of the gate driver should avoid such casualties, but would explain why only the highside FET seems to be affected.

Solution

As the mystery is not fully solved, the following changes were made as a first attempt:

• Changed gate resistors R56/R58 from 4.7 Ohm to 10 Ohm
• Increased dead time to 180 ns (can be measured beween Pin 8 and 5 at U12, measure the time at 0V)
• ordered FETs with higher breakdown Voltage: 750V and 1200V
  Note: The 750V has lower switching losses than the 1200V version. I will go with the 750V version first.

For now, the first tests will be conducted with the current 650V FETs but with altered dead time and 10 Ohm gate resistors.
If there are any news, I will update this text. Also join the discussion in the Issues-Section. I appreciate every idea!

Changes

Documentation

Change	Page
Changed “Vocabulary and list of abbreviations” to “Glossary of Abbreviations”	5
Distinguished between insulation and isolation, other small wording improvements	misc.

Build Guide

Change	Page
Improvement of the description of the secondary windings and their connections.	16
Added fault if enable switch resistance is too high.	29
Added fault when the secondary windings are swapped.	30
Extended note on IR thermometer Measurement inaccuracy	31
Added note about not using 24 V on the output for testing due to the control loop shutting down the converter (which must happen - but is not useful for tests)	28/29

PCB

• Changed Gate Resistors R56/R58 from 4.7 Ohm to 10 Ohm