Ph.D. Candidate in Electrical and Computer Engineering at UMKC
Computer architecture researcher working at the intersection of AI accelerators, hardware–software co-design, compiler-guided workload mapping, and performance modeling. My research focuses on programmable and reconfigurable computing architectures for efficient AI execution, spanning accelerator design, memory organization, workload mapping, and hardware-aware evaluation.
Computer Architecture
AI Accelerators
Hardware–Software Co-design
Mapping & Scheduling
Memory Systems
Reconfigurable Computing
FPGA/ASIC
Hardware Security
⚙️ MAVeCMessage-driven reconfigurable accelerator architecture for AI and data-intensive workloads. |
🔀 InTuiTArchitecture-aware AI workload mapping, scheduling, and performance evaluation framework. |
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FPGA-based hardware acceleration for elliptic-curve cryptography. |
Logic-reuse and energy-efficient arithmetic architectures for vector and accelerator systems. |
◈ OFFLOADFramework for distributing data-intensive and AI workloads across heterogeneous compute units. |
CMOS circuit design and analysis for RF transceiver front-end components. |