Research

Research focused on computer architecture, AI accelerators, hardware–software co-design, reconfigurable computing, and efficient hardware systems.

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Research Projects

MAVeC: Message-Driven AI Accelerator Message-driven reconfigurable architecture for efficient AI and data-intensive workload execution. View Project →	InTuiT Mapper Architecture-aware AI workload mapping, scheduling, and performance evaluation framework. View Project →
FPGA ECC Crypto Engine FPGA-based hardware acceleration for elliptic-curve cryptography. View Project →	Low-Power Arithmetic Logic-reuse and energy-efficient arithmetic architectures for vector and accelerator systems. View Project →
OFFLOAD Framework for distributing data-intensive and AI workloads across heterogeneous compute units. View Project →	CMOS Analog & RF Circuit Design CMOS circuit design and analysis for power management and RF transceiver systems. View Project →

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Research Interests

Computer Architecture AI Accelerators Hardware–Software Co-design Reconfigurable Computing Mapping & Scheduling Performance Modeling FPGA/ASIC Hardware Security Low-Power Design

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Code Availability

Research implementations and development code are maintained privately. Public code, artifacts, and reproducibility resources are released where appropriate.