This is an initial integrated flow of PyLog & HLS4M. PyLog is a Python-based compiler that transforms customized Python code to HLS C/FPGA bitstreams. HLS4ML is a Python package for machine learning inference in FPGAs through carefully hand-tuned HLS IPs. This effort aims to combine the two flow together so that HLS4ML users could use PyLog to generate customized HLS layers and combine them with existing HLS4ML IPs.
PyLog: https://github.com/hst10/pylog/tree/master
HLS4ML: https://github.com/fastmachinelearning/hls4ml
git clone --recursive git@github.com:TimJZ/PyLog-HLS4ML.git