FakeRAM LEF pin direction incorrect

I stumbled upon this while debugging my gate level sim. The fakeram LEFs define the lower bits of `rwN_wd_in` as input, higher bits as output. This lead to my design having the upper bits floating in sim. 

Here's an example:
https://github.com/VLSIDA/HighTide/blob/f294bdc8839355b05c995046a553e24189bd77f4/designs/asap7/eyeriss/sram/lef/fakeram_12x128_1rw.lef#L62