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1. N-Input_Complete_Operators N-Input_Complete_Operators Public

   this is some code to help me determine if a boolean operator is complete

   C++

2. Water_Reminder_CPE302Final Water_Reminder_CPE302Final Public

   SystemVerilog

3. RISC_Processor_CPE300Final RISC_Processor_CPE300Final Public

   SystemVerilog

4. Branch_Predictor_CPE404Project2 Branch_Predictor_CPE404Project2 Public

   SystemVerilog

5. Buck-Converter-C5-Process Buck-Converter-C5-Process Public

6. cvw cvw Public

   Forked from openhwgroup/cvw

   CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

   SystemVerilog