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Add DDR-based MLO support for Zynq devices - #1607

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auphelia merged 30 commits into
Xilinx:devfrom
klassen9:feature/mlo_ddr
Jul 30, 2026
Merged

Add DDR-based MLO support for Zynq devices#1607
auphelia merged 30 commits into
Xilinx:devfrom
klassen9:feature/mlo_ddr

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@klassen9

@klassen9 klassen9 commented Jun 23, 2026

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Extends FINN's MLO flow (loop-based weight offloading via FINNLoop) to store weights and intermediate frames in DDR rather than only HBM, enabling MLO on Zynq-class boards without HBM. Memory placement is selectable via build config, with address offsets generated automatically and threaded through the RTL, Zynq build, and PYNQ driver. The existing HBM path is unchanged by default.

• Build config: new mlo_weight_mem option to select between HBM and DDR
• Address handling: new AssignMemoryOffset transform assigns offsets to weight and intermediate-frame regions in a shared DDR layout. Offset and base-address signals added to fetch_weights/loop_control, plus a new address_config RTL module.
• Zynq build & driver: make_zynq_proj/stitched IP wired up for DDR base addresses. PYNQ driver extended for MLO.
• RTL fixes: byte-aligned intermediate_frames padding, mux prioritizes intermediate frames to fix a batch-size bug, corrected fetch-weight sizing and .dat generation.
• Testing: New end-to-end DDR MLO test plus extended FINNLoop tests covering additional MLO edge cases.

TODO:

  • Rename m_axi_hbm (no longer HBM-specific now that DDR is supported).
  • Merge with dev after PR Feature/tiling mlo #1566 is merged.
  • Some test cases currently fail due to the fetch weight component. At least some of these are fixed by Feature/tiling mlo #1566.
  • Look into tiled MatMul + MLO issues

Misc:

  • Parallel write_bitstream jobs via NUM_DEFAULT_WORKERS
  • verify_step now has a batched argument which allows for real batching

klassen9 added 22 commits June 11, 2026 17:26
Modify build Zynq for DDR MLO
	modified:   finn-rtllib/cdma/cdma_u/axi_dma_wr_u.sv
Fix weight dat file generation for fetch weights
Remove weight file padding in mlo_sim
@klassen9
klassen9 marked this pull request as ready for review July 17, 2026 09:10

@preusser-amd preusser-amd left a comment

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Thanks so much, @klassen9!

Comment thread src/finn/builder/build_dataflow_config.py Outdated
Comment thread tests/fpgadataflow/test_fpgadataflow_finnloop.py Outdated

@auphelia auphelia left a comment

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Overall this looks good to me, let's have a chat about the builder argument vs. node attribute situation and then we can merge this into dev.

@klassen9

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Hi @auphelia

The latest commit contains the changes you requested.

For automatically assigning the FINNLoop's memory type, I added a DataflowBuildConfig resolver that runs within step_assign_ddr_weight_offsets, so no additional build step is needed.

Users can still override this automatic assignment by setting mem_type in the folding config, provided both options are available.

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Thank you @klassen9 ! Looks great and it's amazing that MLO is now also usable for embedded boards.

@auphelia
auphelia merged commit 1c59b6b into Xilinx:dev Jul 30, 2026
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4 participants