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Add parallel functional RTL simulation for MLO - #1644

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klassen9:feature/parallel_mlo_rtlsim
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Add parallel functional RTL simulation for MLO#1644
klassen9 wants to merge 2 commits into
Xilinx:devfrom
klassen9:feature/parallel_mlo_rtlsim

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Adds an optional, parallel RTL-simulation path for verifying MLO. Instead of simulating the full FINNLoop sequentially, where every loop iteration runs one after another through the intermediate-frames path, this path builds a lightweight stream tap + body stitched IP and simulates all loop iterations concurrently (one process per iteration), plus the boundary (non-loop) regions separately. This substantially cuts verification time for MLO models.

Since functional verification only needs to check each iteration against a known golden frame, the parallel build drops the intermediate_frames block entirely. Iterations become fully independent and are fed their golden input frame + index directly. However, this might therefore not show any issues caused by the intermediate_frames block during simulation.

The nodes outside the loop are handled by treating each FINNLoop as a cut point and recovering the remaining maximal connected subgraphs. Each boundary region is rebuilt as a standalone model, stitched, and rtl-simulated end-to-end against the same golden context.

This PR is dependent on #1607

klassen9 added 2 commits July 27, 2026 17:34
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