Image Processing and Frame Buffer
The image processing for this project is simple and consists of overlaying a 8x8pixel gray square at an arbitrary address in the frame buffer. To do this a filter is used to determine if the frame buffer is writing to the address of the gray square. A multiplexor is controlled by 8 comparators, one for each line in the square. Only 8 comparators are needed because the three least significant bits of the address are ignored since each case would yield the same true result.
If one of the comparators returns true, a constant gray value is passed through the multiplexor. If none of the comparators return true then the composite input data is passed through the multiplexor and into the frame buffer. A netlist for the image processing can be seen in the image below.
The frame buffer memory for this project is an on chip ram generated by an Altera megafunction. The frame buffer is a two port ram with separate clocks for reading and writing so that the VGA output and the image processing may work at different rates. The read ports are not registered because the Altera megafunction does not require them to be, allowing reads to happen in a single clock cycle. The write ports are registered so writes may only happen on the rising edge of a clock.
Terasic. (2012, May 23). DE2 TV Decoder (Version 2.0) [Computer software]. Retrieved April 21, 2016.