Command and Data Queue

These queues will sit between a CPU module and the Flash Interface module. The queues will feed the Flash Interface with state commands as well as data for the DQ bus. The data may not pass through the Flash Interface module but control signal for the queue will.

Initial Requirements - Could Change

These modules are not designed just yet but here are some assumptions I have made based on the requirements of the Flash Interface module.

• separate queues for flash modes and for data input
• mode queue will be a fifo
• data queue will be a fifo, if the fifo is not empty a read request will be made ASAP so that the byte is available in the first state of a data/address/command input.
• Logic is needed to make the first read request independent of the current flash mode so if the data queue is empty when more data is added that data becomes available.
• It will be the CPU's responsibility to make sure the proper data byte is being output of the queue. It may take an extra cycle to output the right byte if the queue was previously empty.
• The data queue will have underflow checking circuitry. Underflow protection is needed because a read request after reading each, even the last byte.

The repeat counter

To make the Mode Queue more memory efficient, each mode command will have a repeat counter attached to it. The next mode command should not be loaded until the counter is decremented to zero.

The repeat counter should not increase the latency of the mode command queue.