Flash Interface

To get started, I am working with Micron's MT29F32G08CBACAWP:C and MT29F32G08CBADAWP:D. These are 32Gbit MLC nand flash chips with 8 bit asynchronous interfaces. I chose them because they were relatively cheep and available in small quantities at the time. Interfacing with the asynchronous interfaces on these devices should also be easier (but slower) than working with a synchronous interface.

Flash Interface Module Description

###This module should should:

• set the appropriate controls signals on the flash depending on the current mode of the flash.
• set appropriate signals so the CPU module will know when to latch input or output data

This module does not:

• generate commands such as 'read status' or 'program page'
• this module will probably not be responsible for latching the DQ bus. This will be done by a CPU module of some sort to eliminate latency.

FSM Description

Most of this module consists of a Finite State Machine. A state exists for each 'mode' of the flash:

• Standby
• Bus Idle
• Command Input
• Address Input
• Data Input
• Data Output/Data Output End
• Write Protect

Some modes have more than one state e.g. COMMAND_INPUT_0 and COMMAND_INPUT_1. For most of the stats this is because data is latched on the rising or falling edge of a control signal. For a command input, the 0 state sets the WE# signal low and the 1 state sets WE# high.

Repeat Counter Logic Description

Mode commands will be input with a number of time to be repeated.

Signals (incomplete):

• mode_done: this signal is set HIGH during the last state of each mode command. It is used to keep track of the number of repeats and request a new mode command when the repeat counter is 0.
• repeat_counter: this signal is input from the CPU with mode commands. It is latched into c the cycle after the ack_read_mode signal is HIGH.
• c: this signal stores the number of repeats remaining before a new mode command should be requested
• new_command: this signal stores the buffered ack_mode_read signal. It indicates that the command and repeat counter data is different this clock cycle than last clock cycle.

Each time a mode command finishes, the mode_done signal is set HIGH and counter variable c is decreased by one. If c is equal to 0 then the mode_done signal is allowed to set the ack_mode_read signal to load the next mode command. The ack_mode_read signal is buffered for one clock cycle with the new_command signal. The new_command signal indicates that the current mode command's repeat counter can be latched into c.

Notes

A data output sequence should be ended with the data_output_end_0 mode. This means that a series of data_output_0 modes should be followed by a data_output_end_0 mode.