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Aria v1.4.0
What's Changed
- Added model-profile checks for graph wiring, Dense structure, fixed-point formats, and coefficient patterns.
- Added automatic selection of the sequential packed Dense weight ROM for compatible models.
- Preserved compatible Dense plans during project refresh and rejected unsupported structural changes explicitly.
- Updated the manifest to record semantic model facts and the resolved Dense implementation plan.
- Qualified the default P4/D2 flow with Vitis HLS 2023.2 synthesis, RTL CoSim, and KU5P OOC implementation.
The default P4/D2 build achieves II 94 and latency 99. At 200 MHz, the routed single core uses 1.5 BRAM tiles, 15 DSPs, 3,622 registers, and 6,981 LUTs, with +0.524 ns WNS.