Aria v1.7.2

What's New

Aria 1.7.2 improves throughput and resource efficiency for multi-convolution streaming designs with shared arithmetic optimization and target-aware search.

• Applies CSD/CSE constant-arithmetic optimization to both convolution stages, reducing repeated calculations and supporting mixed LUT/DSP implementations.
• Adds Optimization.TargetII to guide automatic selection toward lower estimated LUT usage while meeting the requested throughput.
• Improves convolution scheduling and introduces compute-unit reuse across spatial positions.
• Expands validation with RTL co-simulation, streaming protocol tests, and routed single-core timing checks.

Aria v1.7.1

What's New

Aria 1.7.1 introduces automatic optimization search for multi-convolution streaming designs, improving throughput within the selected P/D configuration.

• Derives convolution schedules and spatial parallelism candidates from model geometry and data dependencies.
• Evaluates stage throughput, stream packing, and resource estimates together to select supported implementations.
• Records search decisions and the selected architecture for reproducible conversion.

Aria v1.7.0

What's New

Aria 1.7.1 introduces automatic optimization search for multi-convolution streaming designs, exploring schedules and parallelism within the selected P/D configuration.

• Derives convolution schedules and parallelism candidates from model geometry and data dependencies.
• Optimizes stream packing and stage throughput together to reduce whole-model bottlenecks.
• Records the selected implementation, search decisions, and validation evidence for reproducible conversion.

Aria v1.6.2

What's New

Aria 1.6.2 improves correctness and verification reliability for P2 streaming conversions, including 7x1 kernel, stride-2 models.

• Corrects P2 convolution window scheduling for supported kernel and stride combinations.
• Adds schedule validation and position-sensitive verification inputs to catch alignment errors.
• Verifies generated projects in a fresh process and improves linked-project compiler reliability.

Aria v1.6.1

What's New

Aria 1.6.1 improves Keras/HGQ2 input compatibility and generated-project reliability for streaming conversion, including models that expose the singleton channel dimension directly.

• Accepts direct (height, width, 1) Keras inputs and normalizes them to the canonical (height, width) -> Reshape(height, width, 1) streaming interface.
• Handles fusible fixed-point activation quantizers introduced by the hls4ml bit-exact flow without misclassifying a source-homogeneous HGQ2 model as heterogeneous.
• Accepts supplied verification inputs shaped (samples, height, width, 1) and records their canonical (samples, height, width) form.

Aria v1.6.0

What’s New

Aria 1.6.0 introduces PHARA, a pool-aligned P8/D4 architecture that substantially improves throughput while preserving bit-exact model behavior.

• Adds P8 temporal packing and Dense D4 parallelism as the new aggressive default.
• Fuses convolution, ReLU, and MaxPool into a pool-aligned processing region.
• Uses hybrid CSD/CSE and DSP constant arithmetic with symbolic modular equivalence proofs.
• Adds row-credit scheduling for bounded buffering and input backpressure.

For the reference four-channel, 8-bit input format, one PHARA core processes 40.1 Gb/s of raw input at the timing-estimated 249.8 MHz. A 16-core KU5P estimate reaches 642 Gb/s while remaining below 70% DSP utilization. Multi-core routing and board-level validation remain separate.

Aria v1.5.1

What’s New

Aria 1.5.1 stabilizes first-convolution performance across models with different trained weights and sparsity.

• Adds sparsity-independent, full-width resource planning for the first convolution.
• Prevents learned zero weights from unexpectedly increasing the pipeline initiation interval.

Aria v1.5.0

What’s New

Aria 1.5.0 introduces automatic adaptation for CNN models that share the supported topology but differ in dimensions, trained weights, datasets, or random seeds.

Highlights:

• Dynamically extracts model geometry and parameters from the hls4ml ModelGraph.
• Adds unified analyze, convert, and refresh workflows.
• Introduces immutable model facts and resolved optimization designs.
• Adds .ravelparams v2 for portable compiled parameter packages.
• Improves configuration validation and unsupported-model diagnostics.
• Records truthful optimization-pass and qualification evidence.
• Removes legacy hard-coded generation paths.
• Validated against 12 retrained models, including RTL cosimulation for three representative variants.

Qualification checks conversion consistency with the source model.

Aria v1.4.0

What's Changed

1. Added model-profile checks for graph wiring, Dense structure, fixed-point formats, and coefficient patterns.
2. Added automatic selection of the sequential packed Dense weight ROM for compatible models.
3. Preserved compatible Dense plans during project refresh and rejected unsupported structural changes explicitly.
4. Updated the manifest to record semantic model facts and the resolved Dense implementation plan.
5. Qualified the default P4/D2 flow with Vitis HLS 2023.2 synthesis, RTL CoSim, and KU5P OOC implementation.

The default P4/D2 build achieves II 94 and latency 99. At 200 MHz, the routed single core uses 1.5 BRAM tiles, 15 DSPs, 3,622 registers, and 6,981 LUTs, with +0.524 ns WNS.

Aria v1.3.0

What's Changed

• update README by @albertc9 in #7
• update readme by @albertc9 in #8
• update readme by @albertc9 in #9
• v1.3.0 by @albertc9 in #10

Full Changelog: v1.2.4...v1.3.0

1. Optimization now supports independent selection of P2/P4 and Dense x1/x2
2. When Optimization is not specified, generate.py defaults to P4/D2.
3. P2/D1 remains available as an explicit fallback; refreshing legacy Aria 1.1 projects also preserves P2/D1.
4. All four combinations pass the required conversion verification.
5. The default P4/D2 configuration successfully completes Vitis HLS 2023.2 synthesis and Verilog RTL CoSim with 32 samples.

II was reduced by 47.2%, reaching the expected range of 84–95. Resource usage did not decrease: LUT usage increased by 85.0%, but still accounts for only 24.66% of the KU5P. This is the main cost of doubling the per-cycle computation in the Dense layer. Cyclic weight partitioning was also evaluated; although it reduced LUT usage to 20,109, II degraded to 129 and DSP usage increased to 64, so this approach was not adopted.