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Aria v1.6.0

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@albertc9 albertc9 released this 13 Aug 02:31
· 65 commits to main since this release
v1.6.0
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What’s New

Aria 1.6.0 introduces PHARA, a pool-aligned P8/D4 architecture that substantially improves throughput while preserving bit-exact model behavior.

  • Adds P8 temporal packing and Dense D4 parallelism as the new aggressive default.
  • Fuses convolution, ReLU, and MaxPool into a pool-aligned processing region.
  • Uses hybrid CSD/CSE and DSP constant arithmetic with symbolic modular equivalence proofs.
  • Adds row-credit scheduling for bounded buffering and input backpressure.

For the reference four-channel, 8-bit input format, one PHARA core processes 40.1 Gb/s of raw input at the timing-estimated 249.8 MHz. A 16-core KU5P estimate reaches 642 Gb/s while remaining below 70% DSP utilization. Multi-core routing and board-level validation remain separate.

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