Tricore sched optimization #17904
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Tricore sched optimization #17904
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…he CSA. In the exception panic process, regs needs to use a memory address, which defaults to PCXI. Here, it is uniformly saved as the actual memory address. Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
with other functionalities removed. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
zhangyu-duck
requested review from
anchao,
davids5,
jerpelea,
johannes-nivus,
raiden00pl and
simbit18
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Area: Tooling
Arch: tricore
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Summary
Optimize tricore arch task switching process, now most other archs have already implemented task switching optimizations, such as:
Directly using tcb->xcp.regs instead of up_current_regs to determine whether to switch tasks.
Removing interfaces like up_set_current_regs/up_current_regs.
Inlining up_switch_context, etc.
For ARM implementation references:
03af486
4972a8e
Impact
The logic during doirq.c and svcall.c for determining whether a task needs to be switched has changed;
The interrupt flag interface has changed.
Testing
Run ostest multiple times and observe whether the task switch is normal.
The main test items in ostest:
task create/exit/restart.
semaphore wait/post test
message queue test
signal process test
wdog test
...