{bp-19177} stm32h5/qspi, drivers/mtd/gd25: add QSPIMEM_QUADDATA flag and GD25 QSPI support#19276
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Add QSPIMEM_QUADDATA to the QSPI memory flags. This flag selects quad data width while keeping the address phase on a single line (1-1-4), which QSPIMEM_QUADIO cannot express (it forces quad on both address and data phases). Update stm32_qspi_memory() to honour the new flag by setting CCR_DMODE_QUAD without touching the address mode. Signed-off-by: Sammy Tran <sammytran@geotab.com>
Add QSPI mode to the GD25 MTD driver alongside the existing SPI path. When CONFIG_GD25_QSPI is selected, sector erase, chip erase, byte read, page write, and byte write all use the QSPI command/memory interfaces instead of SPI. Reads use the quad I/O fast-read command (1-4-4) and writes use the quad page-program command (1-1-4) via QSPIMEM_QUADDATA. A new Kconfig option enables the QE bit in SR2 at initialisation so the quad I/O pins are active. Signed-off-by: Sammy Tran <sammytran@geotab.com>
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Summary
include/nuttx/spi/qspi.h currently has QSPIMEM_QUADIO for 1-4-4 transfers (address and data both on quad lines) but no way to express 1-1-4 (single-line address, quad-width data only). Several NOR flash devices use this mode for page program commands.
This adds QSPIMEM_QUADDATA (bit 1) and QSPIMEM_ISQUADDATA() to fill that gap, and extends the STM32H5 QSPI driver to set CCR_DMODE_QUAD when either QUADIO or QUADDATA is set. The address-mode selection block is unchanged, so QUADDATA keeps addrmode at single-line.
The GD25 MTD driver is updated as the first user, gaining a CONFIG_GD25_QSPI build option that switches it from SPI to QuadSPI. When enabled, gd25_initialize() accepts a qspi_dev_s pointer and a bool unprotect. Both 3- and 4-byte address modes are supported, and the existing SPI path is fully preserved when CONFIG_GD25_QSPI=n.
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