v2.0.2: TUI Navigation Cache Hit Stability Hotfix

SimRV v2.0.2

Maintenance release fixing an issue where browsing TUI tool pages unintentionally incremented instruction cache hit counters.

Bug Fixes

• TUI Navigation Stability: Fixed an issue where switching between tool tabs or opening the Instruction Explainer caused extra I-Cache hits to be recorded without executing instructions.

v2.0.1: Cache Accounting Hotfix & Study Session

SimRV v2.0.1

Maintenance release addressing cache hit/miss accounting accuracy, TUI cache inspector highlights, and introducing interactive cache technology study session guides.

Bug Fixes

• Cache Hit/Miss Accounting: Fixed an issue where data refills after a cache miss were incorrectly recorded as hits, ensuring accurate hit rates and miss penalties.
• TUI Cache Inspector: Improved cache line highlighting so current hits are clearly visible without being obscured by previous replacement markers.

Educational Guides & Workloads

• Added comprehensive 60-minute Cache Technologies study sessions in English (docs/STUDY_SESSION_CACHE.md) and Japanese (docs/STUDY_SESSION_CACHE_JA.md) covering spatial and temporal locality, set associativity, conflict thrashing, and multicore coherence (MESI/MOESI, false sharing).
• Added pre-compiled bare-metal RISC-V workloads and sources in examples/study_session_cache/ and /mnt/archlab/study/cache/.

SimRV v2.0.0: Dual-Width Explainable RISC-V System Simulator (General Availability)

SimRV v2.0.0 General Availability Release

SimRV 2.0 is a cycle-oriented, full-system RISC-V simulator engineered in ISO C++23 that bridges high-throughput functional simulation, microarchitectural explainability, and in-terminal visual inspection.

---

Key Capabilities & Architectural Pillars

1. Zero-Overhead Dual-Width Modularity: Compile-time parametric design (SIMRV_XLEN) for both RV32GCBV and RV64GCBV profiles without runtime polymorphic branching or virtualization penalties.
2. High-Throughput Fast Execution Path: Direct decode caching (CachedOp), branchless register commit, and direct M-mode DRAM filtering delivering 195+ MIPS on CoreMark with an overall 1.66x geometric mean speedup over Spike across a 20-run statistical evaluation.
3. First-Class Pipeline Explainability Engine: Cycle-by-cycle tracking across a 5-stage pipeline (IF, ID, EX, MEM, WB), operand forwarding analysis, dynamic hazard classification (RAW/WAR/WAW), and automated natural-language causal reasoning.
4. Interactive In-Terminal Visual Inspection: Split-screen TUI powered by an internal ANSI/VT100 Virtual Terminal and hardware Sixel graphics protocol, streaming guest graphical framebuffers over headless SSH sessions with zero host X11/Wayland/SDL dependencies.
5. Full-Stack OS & Multi-RTOS Platform: Direct execution of upstream RISC-V Linux kernels (v6.x/v7.x), μT-Kernel 3.0 (verified in fork), and embedded RTOS payloads over standard MMIO peripherals (VirtIO Block, NS16550 UART, CLINT, PLIC, RTC, and TileLink crossbar).

---

Verification Summary

• RV64 CTest Gate Suite: 368 / 368 passed (100%).
• RV32 CTest Gate Suite: 274 / 274 passed (100%).
• Spike Lockstep Co-Simulation: 100% agreement with zero instruction divergences.
• Code Quality: clang-format verified cleanly across all targets; all 13 CI matrix workflows green.

v2.0.0-rc.9

SimRV 2.0.0 RC9

v2.0.0-rc.8

Release candidate 8: micro-architectural simulation acceleration

v2.0.0-rc.7

Release Candidate 2.0.0-rc.7: High-throughput inlined dispatch engine…

v2.0.0-rc.5

style: apply clang-format to entire C++ codebase

v2.0.0-rc.3

Release v2.0.0-rc.3

v2.0.0-rc.2

Release v2.0.0-rc.2

v2.0.0-rc.1

release: bump to v2.0.0-rc.1 and add CHANGELOG