SimRV v2.0.0: Dual-Width Explainable RISC-V System Simulator (General Availability)
SimRV v2.0.0 General Availability Release
SimRV 2.0 is a cycle-oriented, full-system RISC-V simulator engineered in ISO C++23 that bridges high-throughput functional simulation, microarchitectural explainability, and in-terminal visual inspection.
Key Capabilities & Architectural Pillars
- Zero-Overhead Dual-Width Modularity: Compile-time parametric design (
SIMRV_XLEN) for both RV32GCBV and RV64GCBV profiles without runtime polymorphic branching or virtualization penalties. - High-Throughput Fast Execution Path: Direct decode caching (
CachedOp), branchless register commit, and direct M-mode DRAM filtering delivering 195+ MIPS on CoreMark with an overall 1.66x geometric mean speedup over Spike across a 20-run statistical evaluation. - First-Class Pipeline Explainability Engine: Cycle-by-cycle tracking across a 5-stage pipeline (IF, ID, EX, MEM, WB), operand forwarding analysis, dynamic hazard classification (RAW/WAR/WAW), and automated natural-language causal reasoning.
- Interactive In-Terminal Visual Inspection: Split-screen TUI powered by an internal ANSI/VT100 Virtual Terminal and hardware Sixel graphics protocol, streaming guest graphical framebuffers over headless SSH sessions with zero host X11/Wayland/SDL dependencies.
- Full-Stack OS & Multi-RTOS Platform: Direct execution of upstream RISC-V Linux kernels (v6.x/v7.x), μT-Kernel 3.0 (verified in fork), and embedded RTOS payloads over standard MMIO peripherals (VirtIO Block, NS16550 UART, CLINT, PLIC, RTC, and TileLink crossbar).
Verification Summary
- RV64 CTest Gate Suite: 368 / 368 passed (100%).
- RV32 CTest Gate Suite: 274 / 274 passed (100%).
- Spike Lockstep Co-Simulation: 100% agreement with zero instruction divergences.
- Code Quality: clang-format verified cleanly across all targets; all 13 CI matrix workflows green.