release_v20231111_0

Work-around timing-out verilator-nightly tests (#1058)

* driver tests: Reduce number of iterations of test_sha1.

This test times out under verilator. By reducing the number of
iterations it can pass.

* Don't run ecdsa_cmd_run_wycheproof() test in verilator nightly.

This test is too slow to run without timing out. It will still run on
the FPGA and sw-emulator.

* Don't run slow ROM validation tests in verilator nightly.

These tests are too slow to run without timing out. They will still run
on the FPGA and sw-emulator.