v1.2.3

Bug

This release contains #1270, which unfortunately introduced issue #1426.

API Modification

(#1294) Make EmittedAnnotation Unserializable (bp #1288)
(#1342) add IsModule, IsMember, CompleteTarget serializers (bp #1321)

Fix

(#1283) Fix incorrect ScalaDoc link (bp #1282)
(#1352) Fix conversion of Reference-containing expressions to ReferenceTargets (bp #1349)
(#1369) Better register const prop through speculative de-optimization (bp #1366) - fixes #1240
(#1386) Fixing lint error: x + -1 (bp #1374)
(#1398) Remove last connect semantics from reset inference (bp #1396)

Feature

(#1285) Improve Scaladoc (bp #1284)
(#1295) Verilog emitter transform InlineNots (bp #1270)
(#1299) Cleanup verilog emitter casts (bp #1264)
(#1303) Dedup PassTests, add NoCircuitDedupAnnotations (bp #1302)
(#1306) Change default LogLevel to Warn (bp #1305)
(#1313) Filter ResolvePaths in EliminateTargetPaths (bp #1310)
(#1314) Verilog emitter transform InlineBitExtractions (bp #1296)
(#1318) Refactoring checkCatArgumentLegality (bp #1317)
(#1353) Dedup: check if moduleOpt exists before getting (bp #1323)
(#1360) Emit 'else' case for trivial-valued async reset regs to avoid latches (bp #1359)
(#1363) Add constant prop to async regs (bp #1355)
(#1373) Rename Modules Duplicated by EliminateTargetPaths (bp #1370)
(#1384) Add reviewer checklist / update contributor checklist (bp #1375)
(#1385) Support MemConfs with very deep memories (bp #1367)
(#1395) Constant prop binary PrimOps with matching arguments (bp #1361)
(#1402) Add more docs / tests for DiGraph reachableFrom method (bp #1401)