Interrupts and Timers

Interrupts & Timers

The kernel is interrupt-driven, so the timing peripherals aren't optional — without them the shell boots and then waits forever for events that never arrive (see Boot Sequence).

Interrupt model

There are 11 interrupt sources with fixed vector addresses in the internal ROM and a strict priority order:

Priority	Source
highest	DMA complete	a blit finished
	Timer 0
	External
	UART	the "Web Link" serial port (not emulated)
	LCD (vblank)	once per frame
	Timer 1	the kernel's main heartbeat
	Clock	the real-time clock tick
	PIO
lowest	Watchdog / NMI / illegal-op	non-maskable

Delivery is gated by three things: the source's enable bit (IE0/IE1), the global interrupt flag (PS1.I), and a priority threshold encoded in PS0. On entry the CPU pushes PC and PS1, clears the interrupt flag, and vectors; IRET restores them.

The one that bites: drop-if-masked

This is the subtle bit that derails emulators. When an interrupt source fires while interrupts are masked, the request is dropped, not queued. It is tempting to "latch" pending requests so they fire the moment interrupts are re-enabled — but that's wrong for this hardware, and it shows up immediately: the kernel enables interrupts at a precise point during init, and a spurious latched interrupt arriving right then sends it down a wrong path. Match the hardware (drop while masked) and the boot runs; latch and it derails.

Timers

Two general timers (TM0, TM1) each have an 8-bit prescaler-selected divisor and an up-counter with a programmable reload. When the counter passes its reload value it wraps and raises that timer's interrupt (if enabled). Timer 1 is the kernel's heartbeat — its interrupt service routine drives the menu animation and the event queue, so a game that "boots but never animates" usually means the timers aren't ticking.

There's also a separate real-time clock that ticks once per second (or per minute) and raises the clock interrupt — this is the wake that resumes the startup clock-stabilization STOP.

Because the timer rates derive from the CPU clock, and per-instruction cycle counts on this CPU are only approximate (see The SM8521 CPU), interrupt timing is the main remaining accuracy frontier. It's good enough to boot and run; nailing exact game speed needs a real cycle table.