Memory and the MMU

Memory & the MMU

The SM8521 has a flat 16-bit (64 KB) address space, but the interesting part is the bank-paged region in the middle that maps the much larger system and cartridge ROMs into view.

Address space

Range	Contents
0x0000–0x000F	working registers r0–r15 (banked through PS0)
0x0010–0x007F	I/O and peripheral registers (ports, MMU, LCD, DMA, sound, timers)
0x0080–0x03FF	internal RAM (~1 KB)
0x1000–0x1FFF	internal boot ROM (4 KB); the interrupt vectors live here
0x2000–0x9FFF	four 8 KB paged windows (MMU1–MMU4)
0xA000–0xDFFF	VRAM — write-only to the CPU (reads return 0); see [[Video: VRAM & the DMA blitter
0xE000–0xFFFF	extended I/O + battery-backed RAM

The MMU

Five bank registers (MMU0–MMU4, at 0x24–0x28) each hold an 8 KB page index. MMU1–MMU4 page the four windows from 0x2000 to 0x9FFF; MMU0 covers the internal ROM window and is essentially never touched.

The page index selects between two ROMs:

• Pages 0x00–0x1F → the external kernel ROM (32 pages × 8 KB = 256 KB).
• Pages 0x20–0xFF → the cartridge.

So page << 13 is the byte offset, and the kernel begins below 0x20 while cartridge banks start at 0x20. This boundary is a common source of "the cartridge loads at the wrong offset" bugs — get it off by one and nothing runs.

Bank-switching bugs are the single most common cause of a game-specific failure: the kernel and games re-page these windows constantly, so the paging math has to be exact.

Cartridges

Cartridge images are raw binaries with no header (the .tgc and .bin extensions are interchangeable). Sizes range from 32 KB up to 2 MB; smaller carts are mirror-filled across the 2 MB window so any bank index reads the right data.

A cartridge only responds when the P3 port's slot-select bits choose its slot and a cartridge is present — the kernel probes the slot this way. If you emulate the cartridge as always-present you can confuse that detection.