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ci(codspeed): move the simulation bench gate to a dedicated self-hosted runner#75

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sedghi wants to merge 2 commits into
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ci/codspeed-self-hosted
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ci(codspeed): move the simulation bench gate to a dedicated self-hosted runner#75
sedghi wants to merge 2 commits into
mainfrom
ci/codspeed-self-hosted

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@sedghi

@sedghi sedghi commented Jul 9, 2026

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Why

CodSpeed simulation mode derives its modeled CPU cache from the physical runner CPU. GitHub's shared runners randomly assign Intel Xeon 8370C vs AMD EPYC 7763, so identical source shifts instruction counts run-to-run and CodSpeed flags "Different runtime environments detected" — the noise behind the phantom regressions we've been triaging. Pinning the OS wasn't enough; the CPU model is the remaining variable.

Change

  • codspeed-bench (the blocking simulation gate) now runs on runs-on: [self-hosted, codspeed-bench] instead of ubuntu-24.04. One fixed box → every baseline and PR run on identical hardware → Simulation is stable.
  • Adds docs/ci/self-hosted-runner.md: box requirements (valgrind, node 22, isolated/pinned CPU), how to register the runner, and the cutover order.
  • Only the simulation gate moves; build/test/dist-size/browser-smoke stay on GitHub-hosted runners. (codspeed-walltime already targets codspeed-macro behind a repo variable — unchanged.)

⚠️ Do not merge until the runner is online

Cutover order matters:

  1. Register + start the self-hosted runner with the codspeed-bench label FIRST (see the doc). If this merges before a runner with that label exists, the codspeed-bench job queues indefinitely.
  2. Merge this.
  3. The main push re-seeds the CodSpeed baseline on the fixed hardware. The first PR comparisons after cutover show a one-time environment shift (old shared-runner baseline vs new fixed head) — expected, self-resolves once the baseline is re-seeded.

Rollback: revert runs-on to ubuntu-24.04.

…d runner

Move the codspeed-bench job off GitHub's shared pool (ubuntu-24.04) onto a
fixed self-hosted runner labeled 'codspeed-bench'. Simulation instruction
counts derive from the runner CPU's cache model, and the shared pool
randomly assigns Intel vs AMD hardware, producing spurious cross-run
'Different runtime environments' deltas. A dedicated fixed box keeps every
run on identical hardware so the gate is stable. Adds docs/ci/self-hosted-runner.md
with the box requirements and cutover order.
@coderabbitai

coderabbitai Bot commented Jul 9, 2026

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⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro Plus

Run ID: 957a5dad-6a4f-4512-93c6-18e3781f4c26

📥 Commits

Reviewing files that changed from the base of the PR and between 9c086c9 and 22d2ec1.

📒 Files selected for processing (2)
  • .github/workflows/pr-checks.yml
  • docs/ci/self-hosted-runner.md
✨ Finishing Touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Commit unit tests in branch ci/codspeed-self-hosted

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@codspeed-hq

codspeed-hq Bot commented Jul 9, 2026

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Merging this PR will not alter performance

⚡ 1 improved benchmark
❌ 1 regressed benchmark
✅ 51 untouched benchmarks
⏩ 66 skipped benchmarks1

Warning

Please fix the performance issues or acknowledge them on CodSpeed.

Performance Changes

Mode Benchmark BASE HEAD Efficiency
WallTime instantiate+destroy JPEGEncoder x50 139.5 µs 148.2 µs -5.84%
WallTime instantiate+destroy JPEGDecoder x50 152.2 µs 136.5 µs +11.52%

Tip

Investigate this regression by commenting @codspeedbot fix this regression on this PR, or directly use the CodSpeed MCP with your agent.


Comparing ci/codspeed-self-hosted (22d2ec1) with main (a88a461)2

Open in CodSpeed

Footnotes

  1. 66 benchmarks were skipped, so the baseline results were used instead. If they were deleted from the codebase, click here and archive them to remove them from the performance reports.

  2. No successful run was found on main (9c086c9) during the generation of this report, so a88a461 was used instead as the comparison base. There might be some changes unrelated to this pull request in this report.

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