A curated portfolio of digital hardware and IC design projects developed during my Ph.D. studies in Electrical & Computer Engineering at the University of Illinois Urbana-Champaign (UIUC).
| Folder | Domain | Key Topics / Features | Languages & Tools |
|---|---|---|---|
Comp_Arch_works |
Computer Architecture | OOO Pipelined RISC-V CPU, pipelined cache, GShare branch prediction, Split LSQ | SystemVerilog |
Digital_IC_Design_works |
Digital IC Design | Fully customed standcell SerDes, CMOS standard cell design, Dual-Edged FF | Cadence Virtuoso |
Each folder contains source code, technical reports, scripts, and simulation results where applicable.