Milestone 2 complete - two microdrives, HyperRAM-backed

Milestone 2 is now complete. Since the last release (M2029, one microdrive on FPGA BRAM), two things changed: the microdrive buffer moved from BRAM to real HyperRAM (M2030-M2032), and a genuinely independent second microdrive was added (M2033-M2035) - mdv1_ and mdv2_ can each be loaded, read, written, and saved without affecting the other, both sharing the physical HyperRAM chip through a small round-robin arbiter. Each drive has its own activity LED and its own synthesized motor hum.

The HyperRAM migration alone found and fixed two real hardware bugs: a fixed-cycle read-back wait calibrated for BRAM's 1-cycle latency silently returned stale data once HyperRAM's much longer latency was in the loop, and the fix for that (a "data ready" handshake signal) first shipped as a one-cycle pulse that didn't work for a same-address cache hit - the exact pattern the Options menu triggers on every return to it. The second microdrive's QNICE-side loading/read-back mechanism is a single generic VHDL component instantiated twice, rather than two hand-written copies - the first time this project parametrized a real piece of logic instead of duplicating it.

This release also includes a fresh R3 build. As with previous releases, the R3 .cor compiles clean (positive timing margins, all constraints met, 0 unrouted nets) but has not yet been tested on real R3 hardware - if you have one, please try it and report back.

See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md / DECISIONES.md in the repository for the full milestone-by-milestone history.

Included

• QL4M65-CoreQL-M2035_r6.cor - the compiled core for MEGA65 R6 (tested)
• QL4M65-CoreQL-M2035_r3.cor - the compiled core for MEGA65 R3 (untested on real hardware)
• main.rom - Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet, see PORTING-PLAN.md Milestone 4)
• back.rom - Toolkit II (TK2)
• blank.mdv - a blank, correctly-formatted microdrive test image (copy it twice under different names to test both drives at once)
• INSTRUCTIONS.md - installation instructions

Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.

Known limitations of this milestone: 128 KB RAM (no expansion yet), QL-native CPU speed only, PAL video only. A physical reset button press or an abrupt power loss still doesn't run any firmware, so writes from the last moment before that can still be lost - the same accepted limitation other M2M cores with background write-back (C64MEGA65's vdrives, AExp's ADF floppy) share.

Next up: Milestone 3 - memory expansion (640 KB / 4096 KB) and CPU speed switching (16 MHz / 24 MHz / Full).