Version 1.0 - selectable RAM and CPU speed

Version 1.0 is here. Since the last release (M2035, two microdrives on HyperRAM, 128 KB only, QL-native speed only), Milestone 3 added selectable RAM size and CPU speed - the last two pieces planned for a first "1.0" - and along the way found and fixed a real architecture mistake.

An early Milestone 3 build put the QL's main, CPU-addressed RAM on the MEGA65's HyperRAM chip, on the assumption that HyperRAM would be needed anyway for the largest RAM size. It compiled clean and passed timing, but hung on real hardware during microdrive LOAD/SAVE. Comparing against two other M2M cores on the same hardware (an unreleased Amiga port that keeps its Chip+Slow RAM entirely in FPGA BRAM, and C64MEGA65's HyperRAM-backed REU, which is only ever touched by its own DMA controller, never the 6502 directly) confirmed the real rule: a CPU's directly-addressed main memory doesn't belong on HyperRAM in this framework - HyperRAM suits DMA-style, latency-tolerant traffic (like the two microdrives), not a bus the CPU blocks on every cycle. RAM went back to FPGA BRAM, measured (not guessed) against this FPGA's real BRAM budget: 1024 KB is the largest size that fits.

What's new in this release:

• RAM: 128k / 640k / 1024k, selectable from the Options menu.
• CPU speed: QL native / 16 MHz / 24 MHz / Full, selectable from the Options menu - the same four speeds the original MiSTer core offers. CPU, video/IO ULA and both microdrives all scale together, so turbo mode speeds up microdrive transfers too. Memory contention timing is only modelled at native speed, exactly like the original core.
• Changing either setting triggers an automatic core reset, no hard reset needed.
• A real bug found during hardware testing: at Full CPU speed, the microdrive motor hum went silent (a fixed-cycle tone period tuned for native speed no longer matched the real-time signal it was measuring once the CPU sped up ~5.6x). Fixed - motor hum is now audible and correctly pitched at every speed.

Everything from Milestone 2 is unchanged and still confirmed working: two independent microdrives (mdv1_, mdv2_) with automatic background SD save, manual or automatic system ROM loading, full keyboard. This release was hardware-tested with real QL software - games, a custom Lisp interpreter needing the 640k RAM option, and a full microdrive load-and-play session at Full CPU speed - all on real MEGA65 R6 hardware, no hangs or regressions found.

This release also includes a fresh R3 build. As with previous releases, the R3 .cor compiles clean (positive timing margins, all constraints met, 0 unrouted nets) but has not yet been tested on real R3 hardware - if you have one, please try it and report back.

See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md / DECISIONES.md in the repository for the full milestone-by-milestone history.

Included

• QL4M65-CoreQL-V1.0_r6.cor - the compiled core for MEGA65 R6 (tested)
• QL4M65-CoreQL-V1.0_r3.cor - the compiled core for MEGA65 R3 (untested on real hardware)
• main.rom - Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet, see PORTING-PLAN.md Milestone 4)
• back.rom - Toolkit II (TK2)
• blank.mdv - a blank, correctly-formatted microdrive test image (copy it twice under different names to test both drives at once)
• INSTRUCTIONS.md - installation instructions

Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.

Known limitations of this version: RAM tops out at 1024 KB (BRAM budget); PAL video only; no mouse, no QL-SD hard-drive support yet. A physical reset button press or an abrupt power loss still doesn't run any firmware, so writes from the last moment before that can still be lost - the same accepted limitation other M2M cores with background write-back (C64MEGA65's vdrives, AExp's ADF floppy) share.

Next up: Milestone 4 - QL-SD (QXL.WIN) hard-drive support.

Milestone 2 complete - two microdrives, HyperRAM-backed

Milestone 2 is now complete. Since the last release (M2029, one microdrive on FPGA BRAM), two things changed: the microdrive buffer moved from BRAM to real HyperRAM (M2030-M2032), and a genuinely independent second microdrive was added (M2033-M2035) - mdv1_ and mdv2_ can each be loaded, read, written, and saved without affecting the other, both sharing the physical HyperRAM chip through a small round-robin arbiter. Each drive has its own activity LED and its own synthesized motor hum.

The HyperRAM migration alone found and fixed two real hardware bugs: a fixed-cycle read-back wait calibrated for BRAM's 1-cycle latency silently returned stale data once HyperRAM's much longer latency was in the loop, and the fix for that (a "data ready" handshake signal) first shipped as a one-cycle pulse that didn't work for a same-address cache hit - the exact pattern the Options menu triggers on every return to it. The second microdrive's QNICE-side loading/read-back mechanism is a single generic VHDL component instantiated twice, rather than two hand-written copies - the first time this project parametrized a real piece of logic instead of duplicating it.

This release also includes a fresh R3 build. As with previous releases, the R3 .cor compiles clean (positive timing margins, all constraints met, 0 unrouted nets) but has not yet been tested on real R3 hardware - if you have one, please try it and report back.

See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md / DECISIONES.md in the repository for the full milestone-by-milestone history.

Included

• QL4M65-CoreQL-M2035_r6.cor - the compiled core for MEGA65 R6 (tested)
• QL4M65-CoreQL-M2035_r3.cor - the compiled core for MEGA65 R3 (untested on real hardware)
• main.rom - Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet, see PORTING-PLAN.md Milestone 4)
• back.rom - Toolkit II (TK2)
• blank.mdv - a blank, correctly-formatted microdrive test image (copy it twice under different names to test both drives at once)
• INSTRUCTIONS.md - installation instructions

Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.

Known limitations of this milestone: 128 KB RAM (no expansion yet), QL-native CPU speed only, PAL video only. A physical reset button press or an abrupt power loss still doesn't run any firmware, so writes from the last moment before that can still be lost - the same accepted limitation other M2M cores with background write-back (C64MEGA65's vdrives, AExp's ADF floppy) share.

Next up: Milestone 3 - memory expansion (640 KB / 4096 KB) and CPU speed switching (16 MHz / 24 MHz / Full).

Milestone 2 phase B - microdrive read/write, complete

Milestone 2, phase B: microdrive write support is now complete. SAVE/DIR/LOAD round-trip correctly on real MEGA65 R6 hardware, and - new since the last release - dirty sectors are now flushed back to the SD card's .mdv file automatically, in the background, with no menu interaction required. The MEGA65's drive-activity LED turns blue while there are unsaved sectors and back to red once they've been written out, so it's obvious when it's safe to power off. Verified with Fase0/tools/mdvcheck.py reporting 0 checksum failures out of 765 on a saved-and-reloaded image, including surviving a real power cycle.

This release also includes a fresh R3 build with all of this. As with the previous release, the R3 .cor compiles clean (positive timing margins, all constraints met, 0 unrouted nets) but has not yet been tested on real R3 hardware - if you have one, please try it and report back.

See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md / DECISIONES.md in the repository for the full milestone-by-milestone history - including two genuinely instructive debugging journeys along the way: a clock-enable-domain strobe bug plus a counter-width overflow that both blocked SAVE from working at all (M2022-M2024), and later a QNICE-bus wait-state timing bug that silently corrupted the very first release's SD flush, found by a byte-level diff against the original image rather than by re-reading the code blind (M2026-M2027).

Included

• QL4M65-CoreQL-M2029_r6.cor - the compiled core for MEGA65 R6 (tested)
• QL4M65-CoreQL-M2029_r3.cor - the compiled core for MEGA65 R3 (untested on real hardware)
• main.rom - Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet)
• back.rom - Toolkit II (TK2)
• blank.mdv - a blank, correctly-formatted microdrive test image
• INSTRUCTIONS.md - installation instructions

Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.

Known limitations of this milestone: one drive (mdv1_) only, 128 KB RAM (no expansion yet), QL-native CPU speed only, PAL video only. A physical reset button press or an abrupt power loss still doesn't run any firmware, so writes from the last moment before that can still be lost - the same accepted limitation other M2M cores with background write-back (C64MEGA65's vdrives, AExp's ADF floppy) share.

Milestone 2 phase B, etapa 1 - microdrive write support

Milestone 2, phase B, etapa 1: microdrive write support (SAVE), on top of the existing read support. SAVE/DIR/LOAD round-trip tested working on real MEGA65 R6 hardware, including saving and reloading a program. The R3 build compiles clean (positive timing margins, 0 unrouted nets) but has not yet been tested on real R3 hardware - if you have one, please try it and report back.

See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md / DECISIONES.md in the repository for the full milestone-by-milestone history (including the two-round debugging story behind this release - a strobe-timing bug and a counter-width overflow, the second one found and simulated by an external model after internal static analysis stalled).

Included

• QL4M65-CoreQL-M2024_r6.cor - the compiled core for MEGA65 R6 (tested)
• QL4M65-CoreQL-M2024_r3.cor - the compiled core for MEGA65 R3 (untested on real hardware)
• main.rom - Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet)
• back.rom - Toolkit II (TK2)
• blank.mdv - a blank, correctly-formatted microdrive test image
• INSTRUCTIONS.md - installation instructions

Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.

Known limitations of this milestone: microdrive writes land in the FPGA's own buffer only - there's no way yet to flush them back to the SD card's .mdv file (next up), one drive (mdv1_) only, 128 KB RAM (no expansion yet), QL-native CPU speed only, PAL video only.

Milestone 2 phase A - microdrive (read-only)

Milestone 2, phase A: one microdrive (mdv1_), read-only, loaded from a .MDV image via the Shell's Options menu. DIR mdv1_ and LRUN mdv1_xxx both tested working on real MEGA65 R6 hardware, including sustained reads of full-size programs.

See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md in the repository for the full milestone-by-milestone history.

Included

• QL4M65-CoreQL-M2021_r6.cor - the compiled core
• main.rom - Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet)
• back.rom - Toolkit II (TK2)
• blank.mdv - a blank, correctly-formatted microdrive test image
• INSTRUCTIONS.md - installation instructions

Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.

Known limitations of this milestone: microdrive read-only (write support in progress), 128 KB RAM (no expansion yet), QL-native CPU speed only, PAL video only.