Version 1.0 is here. Since the last release (M2035, two microdrives on HyperRAM, 128 KB only, QL-native speed only), Milestone 3 added selectable RAM size and CPU speed - the last two pieces planned for a first "1.0" - and along the way found and fixed a real architecture mistake.
An early Milestone 3 build put the QL's main, CPU-addressed RAM on the MEGA65's HyperRAM chip, on the assumption that HyperRAM would be needed anyway for the largest RAM size. It compiled clean and passed timing, but hung on real hardware during microdrive LOAD/SAVE. Comparing against two other M2M cores on the same hardware (an unreleased Amiga port that keeps its Chip+Slow RAM entirely in FPGA BRAM, and C64MEGA65's HyperRAM-backed REU, which is only ever touched by its own DMA controller, never the 6502 directly) confirmed the real rule: a CPU's directly-addressed main memory doesn't belong on HyperRAM in this framework - HyperRAM suits DMA-style, latency-tolerant traffic (like the two microdrives), not a bus the CPU blocks on every cycle. RAM went back to FPGA BRAM, measured (not guessed) against this FPGA's real BRAM budget: 1024 KB is the largest size that fits.
What's new in this release:
- RAM: 128k / 640k / 1024k, selectable from the Options menu.
- CPU speed: QL native / 16 MHz / 24 MHz / Full, selectable from the Options menu - the same four speeds the original MiSTer core offers. CPU, video/IO ULA and both microdrives all scale together, so turbo mode speeds up microdrive transfers too. Memory contention timing is only modelled at native speed, exactly like the original core.
- Changing either setting triggers an automatic core reset, no hard reset needed.
- A real bug found during hardware testing: at Full CPU speed, the microdrive motor hum went silent (a fixed-cycle tone period tuned for native speed no longer matched the real-time signal it was measuring once the CPU sped up ~5.6x). Fixed - motor hum is now audible and correctly pitched at every speed.
Everything from Milestone 2 is unchanged and still confirmed working: two independent microdrives (mdv1_, mdv2_) with automatic background SD save, manual or automatic system ROM loading, full keyboard. This release was hardware-tested with real QL software - games, a custom Lisp interpreter needing the 640k RAM option, and a full microdrive load-and-play session at Full CPU speed - all on real MEGA65 R6 hardware, no hangs or regressions found.
This release also includes a fresh R3 build. As with previous releases, the R3 .cor compiles clean (positive timing margins, all constraints met, 0 unrouted nets) but has not yet been tested on real R3 hardware - if you have one, please try it and report back.
See INSTRUCTIONS.md (attached below) for exactly where each file goes on the SD card, and CHANGELOG.md / DECISIONES.md in the repository for the full milestone-by-milestone history.
Included
QL4M65-CoreQL-V1.0_r6.cor- the compiled core for MEGA65 R6 (tested)QL4M65-CoreQL-V1.0_r3.cor- the compiled core for MEGA65 R3 (untested on real hardware)main.rom- Minerva 1.98, plain (no QL-SD driver - this core doesn't implement QL-SD yet, seePORTING-PLAN.mdMilestone 4)back.rom- Toolkit II (TK2)blank.mdv- a blank, correctly-formatted microdrive test image (copy it twice under different names to test both drives at once)INSTRUCTIONS.md- installation instructions
Minerva and TK2 are GPL/GNU-licensed and redistributed here on that basis. For other QL ROMs, see https://sinclairql.net/djw/qlrom/index.html.
Known limitations of this version: RAM tops out at 1024 KB (BRAM budget); PAL video only; no mouse, no QL-SD hard-drive support yet. A physical reset button press or an abrupt power loss still doesn't run any firmware, so writes from the last moment before that can still be lost - the same accepted limitation other M2M cores with background write-back (C64MEGA65's vdrives, AExp's ADF floppy) share.
Next up: Milestone 4 - QL-SD (QXL.WIN) hard-drive support.