Skip to content

Restored ports_arch as the source of truth for the Cortex-M ports #590

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
fdesbiens merged 1 commit into from
Aug 9, 2026
Merged

Restored ports_arch as the source of truth for the Cortex-M ports #590

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 9 additions & 2 deletions ports/cortex_m3/ac5/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
Expand All @@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand All @@ -578,6 +583,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
Expand All @@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

Expand Down
5 changes: 4 additions & 1 deletion ports/cortex_m3/ac6/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
Expand Down Expand Up @@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m3/ac6/src/tx_thread_system_return.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -85,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
Expand Down
4 changes: 4 additions & 0 deletions ports/cortex_m3/gnu/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,8 @@
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -543,6 +545,7 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
Expand All @@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand Down
5 changes: 4 additions & 1 deletion ports/cortex_m3/iar/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
Expand Down Expand Up @@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m3/iar/src/tx_thread_system_return.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -83,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
Expand Down
11 changes: 9 additions & 2 deletions ports/cortex_m3/keil/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
Expand All @@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand All @@ -578,6 +583,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
Expand All @@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m33/ac6/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -592,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m33/ac6/src/tx_thread_system_return.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -86,10 +86,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m33/gnu/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -556,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m33/iar/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -592,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m33/iar/src/tx_thread_system_return.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -82,10 +82,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
Expand Down
11 changes: 9 additions & 2 deletions ports/cortex_m4/ac5/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
/**************************************************************************/
Expand Down Expand Up @@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
Expand All @@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
Expand All @@ -578,6 +583,7 @@ unsigned int interrupt_save;

/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
Expand All @@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

Expand Down
3 changes: 2 additions & 1 deletion ports/cortex_m4/ac6/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -545,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
Expand Down Expand Up @@ -593,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}

Expand Down
2 changes: 2 additions & 0 deletions ports/cortex_m4/ac6/src/tx_thread_system_return.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -85,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
Expand Down
3 changes: 2 additions & 1 deletion ports/cortex_m4/gnu/inc/tx_port.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@

// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).


/**************************************************************************/
Expand Down Expand Up @@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else

#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
Expand Down
Loading