AXI4 L1 Cache DV v0.1.0

Initial public release of the AXI4 L1 data-cache design and verification project.

Evidence included in this release:

• 17/17 directed and random Verilator scenarios passing
• 18/18 functional coverage points observed
• 100/100 optional seeded stress executions passing
• 4/4 compile-time mutations detected
• 86.84% raw and 100% reviewed line coverage
• 98.21% branch coverage
• independent C++ cache/reference-memory model self-test passing
• compile-clean UVM phase/TLM collateral with runtime limitations documented
• solver-ready SymbiYosys harness, with local solver execution not claimed

The AXI4 interface is a constrained cache-master subset and this release does not claim protocol, timing, CDC, or silicon signoff.