AXI4 L1 Cache DV v0.3.2

Coverage-integrity release: generated headline metrics, separate baseline/direct-mapped/SECDED structural coverage, reviewed hole classification, consolidated formal/debug documentation, and expanded SECDED-focused stimulus. Baseline cache behavior is unchanged.

v0.3.1 - Formal and Synthesis Evidence Fixes

Highlights

• Fixes the one-way invalid-victim formal assertion so it applies only to the 2-way geometry.
• Adds passing 1-way and 2-way small-geometry bounded safety evidence at depth 20 under the pinned OSS CAD Suite.
• Preserves the canonical 5/5 formal result: three nominal safety/reachability tasks plus two expected mutation failures.
• Replaces an impractical whole-cache Yosys run with an explicitly scoped storage/control geometry proxy for equal-capacity direct-mapped and 2-way comparison.
• Makes release-check regenerate baseline, edge, and direct-mapped coverage evidence and run the synthesis proxy before associativity reporting.
• Revalidates 22/22 named tests, 100/100 stress scenarios, 127/127 C++ trace replays, 55/55 interaction crosses, 19/19 coverage-edge cases, 20/20 associativity checks, 7/7 SECDED RAS points, and 4/4 mutation detections.

Yosys, formal, coverage, and performance results remain open-source verification proxies rather than commercial signoff.

v0.3.0 - SECDED RAS verification

Adds an optional data-SECDED structural variant while preserving the parity baseline. The release includes single-bit correction and scrub, double-bit containment, corrected dirty writeback/maintenance behavior, an independent C++ SECDED model, named assertions, and a 7/7 RAS coverage matrix. Core evidence remains 22/22 directed tests, 100/100 stress scenarios, 127/127 trace replays, 55/55 interaction crosses, and 4/4 mutation detections.

AXI4 L1 Cache DV v0.2.1

AXI4 L1 Cache DV v0.2.1

This patch release refreshes the public verification evidence and documentation for the AXI4 L1 cache DV project.

Highlights

• Added optional coverage-edge lane with byte-strobe lane matrix, set/way toggle sweep, maintenance boundary traversal, and direct-mapped structural coverage runs.
• Added grouped Verilator code-coverage reporting for baseline 2-way, coverage-edge, and direct-mapped variant evidence.
• Added equal-capacity direct-mapped versus 2-way associativity checks and characterization reports.
• Added AXI4 subset compliance appendix, formal evidence report, and hiring-manager debug case study.
• Refreshed README, verification plan, coverage docs, metrics, and curated reports.

Current Reported Evidence

• Directed/random regression: 22 / 22 passing
• Functional coverage: 21 / 21
• Cache interaction cross coverage: 55 / 55
• Optional coverage-edge scenarios: 10 / 10 passing
• Manifest stress: 100 / 100 passing
• C++ trace replay: 127 / 127 passing
• Bug mutations: 4 / 4 detected
• Associativity directed checks: 20 / 20 passing
• UVM runtime smoke collateral: 3 / 3 compatibility scenarios passing
• Baseline design branch coverage proxy: 95.00%
• Baseline reviewed line coverage proxy: 100.00%

These are open-source simulation, assertion, coverage, and characterization results, not commercial AXI compliance, timing, CDC, or silicon signoff.

AXI4 L1 Cache DV v0.2.0

Verification credibility release

This release upgrades the cache project to trace-driven, independently checked verification evidence.

Measured results

• 22 / 22 directed and random regression scenarios passing
• 21 / 21 trace/event-derived feature points covered
• 100 / 100 manifest-driven stress executions passing
• 127 / 127 C++ trace-replay checks passing
• 55 / 55 cache interaction cross bins covered
• 18 named protocol and architectural assertions
• 4 / 4 compile-time bug mutations detected
• 1 / 1 waveform-backed debug case reproduced
• 98.21% raw branch coverage and 59.49% raw toggle coverage

Highlights

• Explicit read/write hit/miss and clean/dirty eviction directed matrix
• Warning-clean Verilator lint and warning-fatal regression compilation
• Independent C++ checking of CPU responses, AXI bursts, replacement, errors, maintenance, and final backing memory
• Deterministic FST/SVG early-WLAST debug case study
• Per-request latency characterization across four backpressure levels
• Split quick/release GitHub Actions gates with report reproducibility checks

UVM remains optional compile-only methodology collateral. AXI behavior is a constrained cache-master subset, and open-source results are verification evidence rather than commercial signoff.

AXI4 L1 Cache DV v0.1.0

Initial public release of the AXI4 L1 data-cache design and verification project.

Evidence included in this release:

• 17/17 directed and random Verilator scenarios passing
• 18/18 functional coverage points observed
• 100/100 optional seeded stress executions passing
• 4/4 compile-time mutations detected
• 86.84% raw and 100% reviewed line coverage
• 98.21% branch coverage
• independent C++ cache/reference-memory model self-test passing
• compile-clean UVM phase/TLM collateral with runtime limitations documented
• solver-ready SymbiYosys harness, with local solver execution not claimed

The AXI4 interface is a constrained cache-master subset and this release does not claim protocol, timing, CDC, or silicon signoff.