Skip to content

AXI4 L1 Cache DV v0.2.0

Choose a tag to compare

View all tags
@ed766 ed766 released this 06 Jul 00:22
v0.2.0
6abfb5d

Verification credibility release

This release upgrades the cache project to trace-driven, independently checked verification evidence.

Measured results

  • 22 / 22 directed and random regression scenarios passing
  • 21 / 21 trace/event-derived feature points covered
  • 100 / 100 manifest-driven stress executions passing
  • 127 / 127 C++ trace-replay checks passing
  • 55 / 55 cache interaction cross bins covered
  • 18 named protocol and architectural assertions
  • 4 / 4 compile-time bug mutations detected
  • 1 / 1 waveform-backed debug case reproduced
  • 98.21% raw branch coverage and 59.49% raw toggle coverage

Highlights

  • Explicit read/write hit/miss and clean/dirty eviction directed matrix
  • Warning-clean Verilator lint and warning-fatal regression compilation
  • Independent C++ checking of CPU responses, AXI bursts, replacement, errors, maintenance, and final backing memory
  • Deterministic FST/SVG early-WLAST debug case study
  • Per-request latency characterization across four backpressure levels
  • Split quick/release GitHub Actions gates with report reproducibility checks

UVM remains optional compile-only methodology collateral. AXI behavior is a constrained cache-master subset, and open-source results are verification evidence rather than commercial signoff.

Assets 2
Loading