AXI4 L1 Cache DV v0.2.1

AXI4 L1 Cache DV v0.2.1

This patch release refreshes the public verification evidence and documentation for the AXI4 L1 cache DV project.

Highlights

• Added optional coverage-edge lane with byte-strobe lane matrix, set/way toggle sweep, maintenance boundary traversal, and direct-mapped structural coverage runs.
• Added grouped Verilator code-coverage reporting for baseline 2-way, coverage-edge, and direct-mapped variant evidence.
• Added equal-capacity direct-mapped versus 2-way associativity checks and characterization reports.
• Added AXI4 subset compliance appendix, formal evidence report, and hiring-manager debug case study.
• Refreshed README, verification plan, coverage docs, metrics, and curated reports.

Current Reported Evidence

• Directed/random regression: 22 / 22 passing
• Functional coverage: 21 / 21
• Cache interaction cross coverage: 55 / 55
• Optional coverage-edge scenarios: 10 / 10 passing
• Manifest stress: 100 / 100 passing
• C++ trace replay: 127 / 127 passing
• Bug mutations: 4 / 4 detected
• Associativity directed checks: 20 / 20 passing
• UVM runtime smoke collateral: 3 / 3 compatibility scenarios passing
• Baseline design branch coverage proxy: 95.00%
• Baseline reviewed line coverage proxy: 100.00%

These are open-source simulation, assertion, coverage, and characterization results, not commercial AXI compliance, timing, CDC, or silicon signoff.