Adds an optional executable dual-RV32 coherent-memory integration lane while preserving the standalone cache closure.
Evidence highlights:
- 24/24 GCC/ISS workloads
- 400/400 executable RTL litmus schedules checked against herd7 allowed outcomes
- 50/50 generated coherent workloads
- 64/64 functional points and 48/48 interaction crosses
- 10/10 formal groups with reachable covers
- 17/17 RTL mutations detected
- 95.28% line and 92.86% branch coverage for coherent integration RTL
- 80/80 measured RTL performance rows
Also adds deterministic architecture, error/reset, litmus, latency, and evidence-matrix SVGs plus an interactive normalized-trace explorer. Results are open-source behavioral verification evidence, not ACE/CHI compliance or commercial signoff.