2026.08

2026.08 highlights

• More ways to build SoCs: Intel Cyclone V/Agilex HPS integration, Gowin AE350 improvements, native AXI/AXI-Lite HyperRAM, and broader framebuffer memory support.
• New hardware building blocks: FPGA temperature monitors, AP Memory PSRAM and Gowin HyperRAM, SPI/parallel LCD, OV5640 camera capture, and I2S audio.
• Better connectivity: packet streams with byte-valid final words, new LiteEth 1000BASE-X/SGMII PHY options, and LitePCIe protocol and DMA improvements.
• More boards and targets, including ModRetro M64/Chromatic, Sipeed Tang Mega 60K, and new Cyclone V/Agilex HPS paths.
• A dedicated release helper and PyPI publishing workflow for the LiteX ecosystem.

See CHANGES.md for the full list of fixes, additions, and ecosystem updates. LiteJESD204B has been renamed to LiteJESD204; the old Python package remains as a temporary compatibility shim.

[> 2026.08, released on September 24th 2026

[> Fixed

• litex/soc/software/bios / boot : Hardened boot manifest and image validation, bounded flash/SD/SATA and serial loads, reserved BIOS SRAM, improved console argument handling, and added optional ROM/SRAM footprint budgets (8fba2ff44, d871906a5, b4f008aa2, b211762f9).
• litex/soc/cores / interconnect : Fixed UART false-start handling, DMA empty/misaligned transfers, PWM clock-domain controls, framebuffer backpressure, ECC overall-parity reporting, and Wishbone cache refill/lane corner cases (c67392b2d, 59fb89991, 2b228c0bf, e7a71fafb, 53f65a8d9, 6a60c5fa7).
• litex/soc/integration / clock : Preserved CSR alignment and explicit SDRAM origins, bounded automatic bus regions, corrected vendor PLL limits and DDR calibration startup, and kept watchdog reset wiring after CRG construction (0b71558e6, 5a409376b, afa26fa15, 85ef110a5, 8adebf90d, 4b3e5acd8).
• litex/build/sim / setup : Sized XGMII simulator buffers for jumbo frames and preserved leading zeros in full repository SHA pins (497541606, d4b14a244).
• litex/soc/software/liblitespi : Made SPI flash quad-enable handling flash-specific to avoid enabling unsupported modes on other flashes (e0a9476e2).
• litex/tools/litex_json2dts_linux : Added mono1 framebuffer DTS support and moved the default framebuffer placement near the end of main RAM when possible (8e9b42fd2, 187bf754c).
• litex/soc/interconnect/csr : Hardened fixed CSR location handling, fixed CSRStatus(fields=...).read() in standalone simulation to return live field values instead of reset values, and preserved explicit CSR gaps in exported layouts (685ba8115, e463d2eb6, fd03f2672).
• litex/soc/interconnect : Validated writable SRAM memory widths to catch unsupported non-byte-multiple configurations early (4149fb257).
• litex/build/gowin : Resolved Gowin toolchain symlinks before deriving tool paths (PR #2469).
• litex/build/lattice/diamond : Emitted false-path constraints for the Diamond backend (ca37a571c).
• litex/build/sim : Finalized Verilator simulation models on exit, restored concise simulation/clock summary reporting, and terminated stalled child processes cleanly on interrupted run scripts (539ba50a8, e685c7a21, deaf0af75, 49a1d68bd).
• litex/build/sim/ethernet : Handled GMII preamble/FCS TX frames on TAP while preserving bare Etherbone frames with preamble-like prefixes (59f129ca2).
• litex/build/xilinx : Lowered 7-Series SDROutput to single-edge flip-flops instead of ODDR(D1=D2) for better open-toolchain compatibility (0bdbc0d42).
• litex/soc/cores/clock : Rejected duplicate clock output domains across vendor clocking helpers (45c457fc6).
• litex/soc/cores/cpu/cv32e41p : Kept the default variant on RV32IM and added CI coverage to avoid the upstream compressed-instruction return-address issue (d86a229ea).
• litex/soc/cores/cpu/vexriscv_smp : Rejected SDRAM configurations without byte masks and staged generated cluster netlists in the build directory (c2120eda8, e1da240ac).
• litex/soc/cores/cpu/neorv32 / femtorv : Fixed NEORV32 downloaded-source reuse, cache-burst Wishbone wiring, NUMA cache and dual-core integration issues, and FemtoRV source/Wishbone read-lane handling (26a4659a2, 1d9774360, 04b5230f6, 63e0f4c16, 0ae8f9a4d).
• litex/soc/interconnect/axi : Fixed AXI down-converter handling of narrow accesses and serialized narrow single-beat bypasses against outstanding transactions (556bba30d, 60bc97ef7).
• litex/soc/integration/soc : Filtered parser options by selected CPU and allowed direct IRQ signal integration (4ed83bd19, 48b832b7e).
• litex/soc/cores/hyperbus : Restored the Wishbone receive drain after the native bus-interface rework and required explicit incrementing bursts to avoid merging adjacent classic Wishbone accesses (b52348307, 5f372ad10).
• litex/soc/software/bios : Kept boot JSON parsing buffers off the stack to reduce BIOS SRAM pressure (6edc2a956).
• litex/soc/software/libliteeth : Hardened netboot packet handling (add101745).
• litex/build : Fixed review-found toolchain, programmer, parser and converter issues across Xilinx, Altera/Lattice, Efinix/Gowin, Anlogic, CologneChip, Microsemi, QuickLogic and simulation backends (0a0bdfa35, ecc03b139, 57f6a431f, b61186362, a9c6d130b, ef0706ab).
• litex/build/openocd / xilinx : Accepted prefixed OpenOCD drscan words, added late Vivado XDC command support, and fixed Xilinx MultiReg false-path target selection (fdf560d47, d9962cc4d, b9449fc60).
• litex/soc/integration/soc : Preserved requested ROM size when loading an init image, avoided linker-region allocation overlaps, and fixed 8-bit CSR accesses (1c126c194, bc88a9292, b62b13bc0).
• litex/soc/cores/hyperbus : Broke the Wishbone burst response loop and refined adjacent Wishbone read/write continuation handling (ce203f40, 854fc352, f23babce).
• litex/soc/software/bios / remote/etherbone : Cleaned serialboot loads on cached CPUs and preserved the Etherbone read return base address during decode (04c30d42, 2816cca5).
• litex/soc/interconnect/stream : Handled last_be during StrideConverter down-conversion to avoid exposing invalid trailing slices from partial final words (a2a62dcc).
• litex/soc/cores/cpu/blackparrot : Disabled the init-array startup hook on BlackParrot and fenced LiteX CSR accesses (2af4f859, f5035dff).
• litex/gen/fhdl/verilog : Preserved Migen combinatorial semantics when assignments contain forward references, added configurable cycle diagnostics, and made dependency collection scale to large designs (fd69861c6, acb25fa66, 224dfe8ea).
• litex/soc/cores/cpu/coreblocks / software : Moved interrupt-controller setup behind a common startup hook and restored PLIC initialization for Coreblocks (5d7bed953, 144a7b99e, 186a8be9f).
• litex/soc/cores/usb_fifo : Fixed FT245 synchronous writes so registered output data is primed before WR#, including TXE pause and bus-turnaround handling (9dbba0987).
• litex/build/sim : Supplied weak no-op Verilator user hooks so default simulator builds link on Darwin/arm64 while remaining overridable (b3ec7c359).
• litex_setup.py / cpu/ibex : Preserved both abbreviated and leading-zero repository SHA pins and corrected Ibex source/options for current Yosys-Slang releases (389681b79, c768f4144, 42af71946, 3b1fc6aa8).
• litex/soc/integration/soc : Hardened bus mapping and peripheral validation for partial point-to-point maps, overlapping decoded slaves, rounded IO regions, byte-addressed Wishbone width conversion, IRQ counts and SPI clock rates, while permitting valid wide CPU IO windows (8d0b441fd, a98127332, 3dac1aae8, f8662f730, df15a96d3, c05dc2252, a84db8875).
• litex/soc/software : Captured and checked SD CMD6 switch status, added the SR1 bit-6 SPI flash quad-enable sequence, and used per-module erase geometry (933061077, a0b0a1383, f4815f43c).
• litex/build/openocd : Made JTAGStream byte reconstruction work with both Jim Tcl 0.11 and UTF-8 Tcl implementations (d995d1e59).
• litex/gen/fhdl/verilog : Preserved nested inlined subtrees during hierarchical Verilog generation so descendant logic is not dropped from the netlist (f6d21b299, f6627e1c2, d60391cea).
• litex/build/lattice/icestorm / gowin/apicula : Corrected IceStorm ABC9/flow3 option separation and made Apicula pass the effective PLL-generated system-clock target to nextpnr instead of its 12MHz fallback (11d783c0c, 871d85007, bc731f0a4).
• litex/build/efinix : Omitted the unsupported FEEDBACK_MODE property from Trion V1 PLL generation while retaining the existing Trion V2, Titanium and Topaz behavior (5f1edbd9c).
• litedram/phy : Kept the selected JEDEC DDR3 CWL/CL values while correcting Nexus write and Artix-7 read alignment, with explicit PHY latency-contract coverage (9e83eeae5, e734a0953, 624444c3f).
• litespi/cscontrol : Kept a newly selected chip-select asserted for the complete transfer when switching between SPI devices (2ef1f5f18).
• litescope/software/cli : Accepted analyzer CSV enum rows with additional fields when resolving captured signals (6bf3b92f2).
• Boards/targets / platforms : Corrected GW5 DDR clock relationships, the MNT RKX7 framebuffer mapping, and the SQRL FK33 200MHz/PCIe differential pin assignments (fe7793d3b, ac4d761ca, 40c8af387).
• litex/gen/fhdl : Emitted negative constants as explicitly signed two's-complement patterns and correctly classified sliced memory-port outputs as wires in hierarchical Verilog (37b75bd46, 65727d65d).
• litex/build/openocd : Recognized the Intel Stratix V instruction register when programming through OpenOCD (a772000d7).
• litex/build/vhd2v : Preserved p_* VHDL generics as instance parameters when mixed-language support bypasses GHDL conversion (5426cd6f4, bf8f72696, 6fc30900a).
• litex/tools/litex_json2dts_linux : Emitted device-tree nodes for every i2cN CSR bus instead of only i2c0 (96dd87600).
• litex/soc/cores/cpu/cva6 : Corrected PLIC sizing/numbering and CLINT timebase metadata, resolved AMOs/LR-SC before the LiteX bus, cut the resulting AXI paths, separated the CSR/MMIO map, marked MMIO non-idempotent, and exported the CPU/MMU/CLINT/PLIC device-tree data (a2e31cbde, 96724ca4e, c7205711e, 53458999d, 055a80a95, 703b782a7, 6179d7425, b9cfc13a1).
• litex/soc/cores/cpu/vexiiriscv : Implemented flush_cpu_dcache() with a Zicbom CBO sweep so BIOS-loaded images reach memory behind write-back caches without a coherent L2 (6c793c27f).
• litex_setup.py : Installed packaging>=24.2 alongside setuptools so current setuptools releases remain compatible with distributions carrying older packaging versions (878c9c0a0).

[> Added

• litex/soc/cores/cpu/gowin_ae350 : Added direct LiteDRAM attachment, Linux device-tree metadata, CPU debug CSR transport, user interrupt inputs, and separate system-clock description for Gowin AE350 integration (945de9ba4, fdafe3d5f, 52e703571, 99250d00f, 8695a0883).
• litex/soc/cores/video / audio / camera : Added SPI LCD control and RGB565 streaming with an ST7789 initialization helper, OV5640 camera control and DVP capture, I2S audio TX/RX, and a parallel RGB LCD PHY alias (1b2f63127, 9251c3298, 90fd1038e, 9a238c8fa, f7a437043, 3c44a5f27).
• litex/soc/cores/ram : Added an AP Memory x16 PSRAM controller and Gowin HyperRAM wrapper (838a85be8, f83e21a67).
• litex/soc/interconnect/packet : Added byte-valid last_be support to packetization and depacketization, with regression coverage for partial final words (7fca6dba7).
• litex/soc/jtag / tools : Added CPU-debug transport on Xilinx JTAG USER chains, exposed the OpenOCD stream port through litex_server, and made remote access timeouts configurable (22eb6e4e2, fa87e1c59, 17d0f09ee).
• litex/build/gowin / cores/clock : Added Gowin programmer cable/channel/location/UID options, generated-clock constraints, and GW5A PLL dynamic phase adjustment (6545fe361, 4d2de4976, a0899585a).
• litex/soc/cores/hwmon / xadc : Added generic FPGA temperature monitor support, Xilinx hwmon conversion metadata/DTS generation, and initial opt-in Gowin/Intel temperature sensor wrappers with regression coverage (14cc60dc1).
• litex/soc/software/libcompiler_rt : Added RV64 count helper routines (a733aaa75).
• litex/soc/integration/export : Added wide CSR field helper support to generated software exports (cc4a2542b).
• litex/soc/cores/hyperbus / integration : Added native AXI/AXI-Lite HyperRAM support, automatic bus-standard argument selection, a SoC-level add_hyperram helper, and optional portable L2 caching across Wishbone, AXI-Lite and AXI SoCs (53727e564, 545985891, d6a73d241, 6365b2f6c).
• litex/soc/integration/soc : Added slave-bus clock-domain crossing support and a SoC reset request hook (4a8ae302e, 973351aa8).
• litex/soc/cores/cpu/cyclonev_hps : Added Intel Cyclone V HPS (hard dual Cortex-A9) hardcore CPU support with H2F-LW/H2F AXI3 masters, F2H AXI3 slave, F2SDRAM Avalon-MM ports and F2H interrupts through direct cyclonev_hps_interface_* atom instantiation (no Qsys), targeting boards where the HPS is pre-booted (e.g. MiSTer/DE10-Nano), with GIC-aware BIOS interrupt support (Cortex-A9 exception vectors + GIC-390 mask/pending/dispatch).
• litex/soc/cores/cpu/agilex_hps : Added Intel Agilex HPS (Agilex 3/5/7 variants, aarch64) hardcore CPU support with H2F-LW/H2F AXI4 masters, F2H AXI4 slave (Agilex 7) and F2H interrupts through a Platform-Designer-generated HPS (+ optional HPS-EMIF LPDDR4) system.
• litex/build/altera/quartus : Added Platform Designer (Qsys) system generation to the Quartus Pro flow (config-dict-driven qsys-script/qsys-generate at build time), used by the Agilex HPS CPU.
• litex/soc/interconnect/avalon : Added Wishbone2AvalonMM bridge (Wishbone Slave to Avalon-MM Master, single-beat) with simulation coverage.
• litex/soc/cores/cpu : Added Loongson GS232 and CDIM MIPS CPU integrations plus Linux toolchain/package support and boot coverage (e90b7e8af, b7ed16b19, af19e210a, 060c51988, 6e5982265, 4a3f398c2).
• litex/sim / soc/cores/cpu/qemu : Added RISC-V QEMU co-simulation CPU support, AXI co-simulation bridge integration, LiteX simulation wiring, and smoke coverage (b92b7f0f8, 464df90e6, 6ff0f1560, 876ddf83e, da55d8846).
• litex/soc/software/bios : Added extensible boot-method registration, documented BIOS configuration flags, reported BIOS SRAM stack margin, and added an option to disable ANSI output (c612a0194, 11a4ddfc0, 11f94eaa6, b26d1096d).
• litex/soc/software/libc : Added strtoull to the picolibc build inputs (65d7aff3e).
• litex/tools/litex_json2dts_zephyr : Added Zephyr SoC node generation mode (a2e1675ca).
• litex/tools/litex_term : Added exit-marker support for scripted terminal sessions (4a699c4c3).
• litex/tools/litex_server : Added DevMem (/dev/mem) interface (--devmem) for direct memory-mapped SoC access from a Hard CPU running Linux (ex Zynq7000, Cyclone V HPS).
• litex/sim / build/sim : Added GTKWave savefile generation, configurable trace timescales, custom Verilator C++ hooks, and custom serial-module clock names (a6b7c22b4, 328da97ab, 58026a9f5, d9e097d7f).
• litex_setup.py : Added LM32 GCC toolchain installation support (9b5d907b9).
• litex/build/xilinx : Exposed open nextpnr arguments in the Xilinx build path and generated rerunnable Xilinx F4PGA flow.json / build_<name>.sh artifacts (6c1f7c5f5, 2ae1fe87f).
• ci : Enabled Microwatt and CV32E41P boot coverage, with dedicated IRQ boot coverage (cfb3c02e3, de10ffc15, d86a229ea).
• README / doc : Added Fedora simulator install notes, linked the LiteX Notes blog, and added LiteNVMe to the listed LiteX cores ecosystem (a35ba0471, b8c4cf47a, 8e4f63ca2).
• litex/soc/cores/dac : Added a sigma-delta DAC core, constant-transition mode, and follow-up cleanup to match the LiteX core structure (8066e5d8, 276eb1db, 7512318e).
• litex/soc/software/libliteeth : Added a LiteEth DHCP client path and UDP broadcast dispatch support (46d916fd, ffdb5ec3).
• litex/soc/software : Added generic init-array startup support for software builds (97ed83b6).
• litex/gen/fhdl/verilog : Added VerilogTime support to emit Verilog $time expressions (0b4d5ded).
• litex/build/altera / litex_setup.py : Exposed the Quartus IP directory as ip_dir and added optional shallow clone-depth support to LiteX setup/CI flows (51e72824, 3e2e9d0d, 00eb3c57, 7b13113d).
• litex/soc/cores/display : Added a configurable scanned hexadecimal SevenSegmentDisplay supporting 7/8-segment outputs, variable digit counts and selectable polarities (5c3509f9d, 41a42e662).
• litex/soc/cores/ram : Added a generic Wishbone bridge for byte-wide asynchronous SRAM, including byte-select writes and configurable bus/SRAM widths (355ff3ab9, 2696ee500).
• litex/build/gowin : Added Windows Gowin toolchain support from WSL with automatic path conversion while retaining native Linux tool discovery (6b7592d0e).
• litex/build/yosys / cpu/ibex : Added Yosys-Slang SystemVerilog import support for Ibex and selected the built-in Slang frontend by default on current Yosys, with an external-plugin compatibility option (9d2b0510c, 11c2fb6fd).
• litex/build/lattice / cpu/zynq7000 : Added native iCE40 DDR tristate support and an openXC7/Yosys/nextpnr path for Zynq-7000 (e5f5519a2, 7e7e1d19e).
• litex_repos.py / README : Registered LiteDSP as a Work-In-Progress ecosystem core, installed it from its main branch and added it to the core/CI overview (bda8a3268, 6acf95906, d3f8bcf9c).
• litex/soc/cores/cpu/veer_eh1 : Added VeeR EH1 CPU support with ICCM boot handling, PIC interrupt initialization, pythondata registration and a follow-up alignment with LiteX integration conventions (1333149d6, f2709aba3, 1b5af403d, 9cd4b7675).

[> Changed

• litex/soc/interconnect/wishbone / ahb : Added optional same-line Wishbone cache read-burst fast paths and response forwarding, kept cache capacity independent of bus width, and made AHB burst preservation configurable (17407283e, 68993b479, be19117a9, 244ef3302).
• litex/soc/integration / software : Added Etherbone MTU selection, custom SDRAM initialization, and CPU/memory cycle benchmarking for LiteX Sim (e3b349a38, fb6c2a1c5, 3114322d9).
• litex/soc/integration/soc : Moved the SoCCore API implementation to soc.py, kept compatibility imports covered, and switched internal imports to the canonical location (8c28012c0, b25fe6e1b, 15a9af65f).
• litex/compat / core aliases : Removed the legacy litex.compat package/hooks and obsolete compatibility aliases after migrating in-tree users to canonical APIs (S7DNA, S7SystemMonitor, UARTInterface, corrected Inferred* spellings, and with_register) (2ebe242f7, f12553d69).
• litex/soc/interconnect/csr : Added explicit CSR read/write signal aliases and switched internal code to the clearer names while preserving compatibility aliases (b8fce7555, 2f4d45657).
• litex/soc/cores/uart : Factored UART core selection for clearer UART integration (b425ca5b5).
• litex/soc/cores/dma : Added explicit byte-swap control for DMA reader/writer paths while preserving legacy defaults, with endianness regression coverage (c4baeb3e, db2678d1a).
• litex/soc/software : Enabled section garbage-collection inputs for smaller software images (ef32c90e1).
• litex/gen/fhdl : Improved write-first memory template generation (737cf2b97).
• litex/gen/fhdl : Unified combinatorial Verilog generation and normalized inout slices before Verilog emission (5b641f517, 5e10ee3fa).
• litex/soc/integration/builder : Clarified export-generation option handling and kept generated export paths explicit in builder configurations (cf9b449fd).
• litex/build/sim : Enabled simulator tracing by default in generated simulation platforms (b8941fbfb).
• litex/soc/cores/cpu/vexiiriscv : Switched to computed ISA mapping and generated interface-width metadata from VexiiRiscv (22ca9041, 71fb0451).
• litex/soc/software / setup/sim : Disabled _FORTIFY_SOURCE in LiteX software builds and improved macOS Homebrew simulator setup handling (3b529e5a, f8dad411).
• litex/soc/interconnect/stream : Restored reset-less endpoint payload registers after fixing the LiteSATA consumer that had depended on invalid payload values (04104800c).
• litex/soc/integration / video : Generalized framebuffer placement and DMA transport across native LiteDRAM, Wishbone and adapted AXI/AXI-Lite buses, added HyperRAM/integrated-RAM support, validation and coherent bus arbitration, and renamed the framebuffer API arguments to reflect regions and DMA ports (20c68a73e, 80dd37dc7, e25bea695, 57eb2dba3).
• litex/soc/software/hyperram : Made BIOS-programmed HyperRAM latency and drive strength configurable per target (053e7fbba).
• litex/build : Explicitly named system and power-on-reset clock domains to avoid implicit CRG naming issues (77cd5bcbb).

[> Ecosystem

• liteeth : Added Gowin GW5 1000BASE-X and UltraScale SelectIO SGMII/1000BASE-X PHY options, jumbo-frame generation and byte-granular UDP stream support; reused LiteX packetization and fixed Etherbone response ports (809588a, 9846162, a4f3743, 40dfb7a, 51130f2).
• litedram : Added GW5 DDR3 quarter-rate support and calibration improvements, ported them to GW2, and fixed DRAM BIST CDC configuration capture (6b497e0, 73386cf, 311a0f7, cef0593).
• litepcie : Expanded experimental PCIe PTM receive support across 7-Series lanes and UltraScale+ Gen2/Gen3/Gen4, preserved RX byte enables across width changes, and fixed requester packet buffering and Wishbone burst-read registration (21f730c, 273841d, cea749e, e00a2dd, 4db1073).
• litex-boards : Added ModRetro M64/Chromatic and Sipeed Tang Mega 60K targets, connected new Gowin video/audio/camera/HyperRAM paths, extended button/switch GPIO options, and added KCU105 SGMII over LVDS and SDCard options (d1a60526, 70f88c9c, ee90b835, 1a8dd825, 565eb65e, 32dd8aa0, cd1b1cc5).
• litejesd204 : Renamed LiteJESD204B to LiteJESD204 now that the core supports JESD204B (8b10b) and JESD204C (64b66b); the litejesd204b Python package remains as a deprecated compatibility shim for two release cycles. Existing checkouts: mv litejesd204b litejesd204 (or re-run litex_setup.py init) and update imports to litejesd204.* (litejesd204#9).
• litex-boards : Fixed several platform/target descriptions, switched targets to exact SDRAM module definitions where appropriate, and added Altera Agilex 5E / brisbaneSilicon BRS-100 GW1NR9 board support (changes).
• litex-boards : Migrated HyperRAM-capable targets to the SoC-level add_hyperram helper and switched 7-Series monitor targets to S7DNA / S7SystemMonitor after LiteX removed compatibility aliases (12f023fc, 6da4c6bb).
• litedram : Fixed DDR4 RDIMM/SK hynix timing and geometry data, added board-backed SDR/DDR3 module definitions, exposed SDRAM byte-mask capability, and adopted LiteX SoCCore/CSR compatibility updates (changes).
• litedram : Updated the standalone generator FIFO UART path to use UARTInterface directly after LiteX removed RS232PHYInterface (04e9834).
• liteeth : Fixed Agilex RGMII builds with the current Agilex PLL, improved DHCP packet handling with TAP/handshake coverage, and adopted LiteX SoCCore/CSR compatibility updates (changes).
• litepcie : Added optional UltraScale+ PCIe Configuration Management interface exposure, fixed 256/512-bit requester descriptor mapping, and adopted LiteX SoCCore/CSR compatibility updates (changes).
• litesdcard : Fixed SD write CRC feedback through pads_out, made generated DMA Wishbone width configurable, and adopted LiteX SoCCore/CSR compatibility updates (changes).
• litespi : Added PUYA/P25Q32H flash support, documented the S25FL-S quad-enable sequence, and adopted LiteX SoCCore/CSR compatibility updates (changes).
• litei2c / liteiclink / litesata / litescope : Updated companion cores for the explicit CSR signal aliases and canonical SoCCore imports where applicable (litei2c, liteiclink, litesata, litescope).
• liteeth / litesata : Removed the remaining test dependency on LiteX stream_sim by moving the required helpers into the local test suites (702b182, 90601aa).
• litenvme : Added LiteNVMe to the LiteX cores ecosystem after its standalone host-core documentation, hardware bring-up notes, and CI/readme polish matured (repo).
• litex-boards : Added Cyclone V/Agilex HPS target paths, Antmicro DDR5 tester boards, GMM-7550 asynchronous SRAM integration and a GateMate A2/Peppercorn option; expanded Alibaba VU13P PCIe/JTAGBone support and exercised the new framebuffer backends (03b2babf, 6da92985, 9ac53c7a, 721cffab, bc73794d, 36c5d0a9, 42f04b9c).
• liteeth : Reworked packet buffering around the MAC boundary, made SRAM packet FIFOs optional, hardened disabled RX/TX behavior, and added packet-aware UDP transmission, IPv4 gateway routing, DHCP lease parsing and opt-in ECP5 RGMII dynamic speed support (bce752c, 83d2e4a, 0e2e654, 2b61a4e, cbf8a14, 110fbea, ab13a8b).
• litedram : Fixed converter subword ordering/repeated chunks and FIFO bypass drain corner cases, gated generated AXI user ports until ready, blocked disabled DMA CSR writers, and tightened DDR3/DDR4/LPDDR4 timing floors (d557a38, b48ab4d, f68051f, 08170e5, 22575b7, 79272ce, b0f1409, ab46a27).
• litepcie : Made requester/completer handling more PCIe-compliant across descriptors, keep masks, attributes, traffic class, split/zero-length reads, ECRC and error completions; reset DMA data converters with their engines, configured exact BAR apertures, accepted PCI revision 1 and exposed a 7-Series Root Port configuration-management path (69ffb37, e4218c5, 7d64094, 14c72a3, 96be580, 310df2f, eaa7d01, 1c5fa0b, 48b2183, 95b18e4).
• litesata : Qualified RX realignment reset with valid data, renamed UltraScale PHYs after their transceivers while retaining legacy imports, and supported multi-FIS IDENTIFY transfers (5db172c, 68af137, 300340d, 3b65641).
• litesdcard : Reset SD cards during initialization when a reset pad is available and accepted read data while the command response is still completing (b0d2771, 243c658).
• litescope : Added enum-aware GTKWave/VCD and hardened Sigrok exports, made subsampler width configurable, and fixed storage-flush samples, trigger-term flushing, repeated captures and grouped signal offsets (801fe56, 5078eca, 74f0a49, f33b4f6, 4dfcbeb, 1870fdf, d605348).
• litespi : Added UltraScale STARTUPE3 primary-flash support, portable DDR tristates and a pin-level flash model; consolidated module/erase metadata and fixed MMAP write/read restart, page-boundary, command-phase and master-length handling (9a529d5, 133abd0, 8c0a248, 8cb6cb4, 320ddd2, dc29516, c954a2f, 8ca711b).
• litei2c : Added clock-stretching and arbitration-loss handling, detected/reported stuck-low and bus-error conditions, and waited for STOP settling and open-drain bus release (bcd8b9c, f6ef27e, ce0bb5d, 4dd0e1d, e39e39d, 81cf75d).
• litenvme : Corrected completion-data byte count and lower-address fields for raw-TLP PCIe PHYs (9d8e305).
• litedsp : Added the Work-In-Progress portable RF/DSP core ecosystem with fixed-point streaming blocks, filters/rate conversion, modulation/FEC/spectral processing, standalone generation, host drivers/GUI, golden-model and Verilator/formal verification, and cross-vendor implementation/timing coverage (repo).
• litex-boards : Supported the Radiona ULX4M LD v2 without DDR3 data-mask pins by requiring an L2 cache, and added Microsoft Azure X930613-001, ALINX AX7035(B) and AliExpress RK XCKU5P platforms/targets (624d8115, 9bce4702, d2dd50c, 544ebaa).
• litedram : Made ECP5 DDR PHY data-mask generation optional for boards where the DM pads cannot share the other DRAM pads' I/O group, while exposing the full-width-write requirement through PHY settings (d38bb74, e1230f4).
• liteeth : Exposed PCS configuration overrides and optional timing buffers at the Artix-7 1000/2500BASE-X MAC boundary (4040d7f).
• litepcie : Fixed completion-buffer sizing, tag retirement and packet rounding; preserved partial/shifted completion tails and downsized DMA descriptor boundaries; retired reader descriptors on completion; and derived/validated 7-Series user-clock configurations (0047f4b, d798356, 2ca518e, 3a8eef1, ea77120, 04a3262, 5b0133a, d9c1da3, f4dbb63, aa88789, 75500a0).
• litepcie : Added a Stratix V hard-IP PHY, refreshed the Cyclone V wrapper, and hardened the Linux driver against out-of-range register access, partially initialized devices, removal with open file descriptors and leaking minor IDs (b6a8b24, 93572c0, 4b15dbc, 8a2f841, 0a6d55b, e65abbd, 90a65b0).
• litedsp : Added motor-control blocks and a PMSM field-oriented-control example, plus audio processing, metering, PDM and I2S/LJ/RJ/TDM interfaces with corresponding drivers, GUI support, documentation and implementation budgets (changes).